DC、Astro设计流程初级手册

suntou

大家好，我在使用Astro2007.03执行Verilogin的时候，出现如下错误，大家有碰到的吗？
Try to use implict global net patterns.
Use VDD as port/net pattern for global power net VDD
Use VSS as port/net pattern for global ground net VSS
VerilogIn: Reading Verilog file

*****  Verilog HDL translation! *****

*****    Start PASS 1 *****

*****  PASS 1 Complete *****
Elapsed =    0:00:00, CPU =    0:00:00

*****  Verilog HDL translation! *****

*****    Start PASS 2 *****
WARNING : Could not create cell lock file, giving up. Pleae check the link command
Error: Cannot create cell ram16x128.CEL. (MW-007)
ERROR : Near line 14: Port connection failed.
Error: Parser error at or near line 14. (MWNL-027)
Error: Verilog parser cannot parse the ./design_data/RISC_CHIP.v source file. (MWNL-047)
Fail to execute command