CMOS BANDGAP REFERENCE IC_Phd_論文

kevinwjs

CHAPTER
1 INTRODUCTION 1
1.1 The Basic Bandgap Reference 1
1.2 Primary Specifications 4
1.3 Impact of the System-on-Chip (SoC) Paradigm 7
1.4 Research Objectives 9
1.5 Synopsis 12
2 ERROR SOURCES 14
2.1 Process Variations and Mismatch 14
2.2 Package Shift 22
2.3 Power-Supply Variations 24
2.4 Load Variations 29
2.5 Temperature Variations 31
2.6 Summary of Error Sources 32
2.7 Synopsis 33
3 TRIMLESS ACCURACY 34
3.1 Trimming 34
v i
3.2 Switching Solutions 36
3.3 Self-Calibration Schemes 39
3.4 Survivor Strategy 41
3.5 Synopsis 58
4 HIGH PSRR 60
4.1 State-of-the-Art Techniques 60
4.2 Proposed Strategy 63
4.3 Synopsis 70
5 LOW OUTPUT IMPEDANCE 71
5.1 Challenges in an SoC Environment 71
5.2 Proposed CMOS Bandgap Reference 73
5.3 Synopsis 85
6 SYSTEM DESIGN 86
6.1 Review of Proposed Techniques 86
6.2 System-Level Issues 90
6.3 Measurement Results 94
6.4 Discussion: Impact of the Survivor Strategy 101
6.5 Synopsis 103
7 CONCLUSIONS 105
7.1 Challenges 105
7.2 Enabling Techniques 108
7.3 Comparison to State-of-the-Art 114
7.4 Conclusions and Recommendations 117
7.5 Future Technical Trends 118
APPENDIX A: ERRORS DUE TO PROCESS VARIATIONS AND MISMATCH 120
vi i
APPENDIX B: REDUCING ERRORS IN FOLDED-CASCODE TOPOLOGIES 123
APPENDIX C: DETERMINING THE MAGIC VOLTAGE 130
REFERENCES