verilog代码求助，太菜鸟，自己搞很久不懂

yyixx

刚学verilog，用vivado设计RS encoder的top，如图，alpha5,10,11,14都是已经写好了，如图，现在代码一直报错，我又不知道错在哪里，求教，

   

        

            
1. module top(
   
2. input [7:0] datain,
   
3. output [15:0] dataout
   
4. );
   
5. wire [3:0]A1, [3:0]B1, [3:0]R1, [3:0]S1, [3:0]R11, [3:0]R12,[3:0]S11;
   
6. alpha5 (R11[3:0], A1[3:0]);
   
7. alpha11 (R12[3:0], B1[3:0]);
   
8. alpha10 (S11[3:0], A1[3:0]);
   
9. alpha14 (S12[3:0], B1[3:0]);
   
10. xor (R1[3:0], R11[3:0], R12[3:0]);
    
11. xor (S1[3:0], S11[3:0], S12[3:0]);
    
12. assign datain[7:0]={A1[3:0],B1[7:4]};
    
13. assign dataout[15:0]={A1[3:0],B1[7:4],R1[11:8],S1[15:12]};
    
14. endmodule
            

   

    复制代码

对verilog和vivado都是在太不熟悉

yyixx

回复 4# harry_hust


   说对了，按楼上改了syntax error是没有了，但综合的时候出错，datain这里的确有问题，请问这里input将8bits数据分成两个4bits数据怎么改？[Synth 8-3352] multi-driven net b14[0] with 2nd driver pin 'GND' ["E:/vivado_project/RS/RS.srcs/sources_1/new/alpha11.v":27]
[Synth 8-3352] multi-driven net b14[0] with 1st driver pin 'i_1/i_3/O' ["E:/vivado_project/RS/RS.srcs/sources_1/new/alpha11.v":27]
[Synth 8-5559] multi-driven net b14[0] is connected to constant driver, other driver is ignored ["E:/vivado_project/RS/RS.srcs/sources_1/new/alpha11.v":27]
[Synth 8-4485] pin datain[7] is connected to multiply driven net where other driver is constant
[Common 17-69] Command failed: Vivado Synthesis failed

前三个warning，后两个是error