how to change VHDL code to get rid of latch's

xiaoyisimonguo

I have the following Vhdl codes for my module: and I want to get rid of the if, which
I believe generated latch. Please help to change to

clk_en_latch: PROCESS(clk_enable, clk)
  BEGIN
    IF clk = '0' THEN
      latched_clk_en <= clk_enable;
    END IF;
  END PROCESS;

I did try to change the code to the following, although I don't have any experience dealing with VHDL code


clk_en_latch: PROCESS(clk_enable, clk)
  BEGIN
    WAIT UNTIL clk'event AND clk='0';
      latched_clk_en <= clk_enable;
  END PROCESS;

but I got the error below, please help,
-------------------
    52:     WAIT UNTIL clk'event AND clk='0';
            ^^^^
[Error] Illegal wait statement: cannot appear inside process with sensitivity list