运行uvm时出现it is not registered with the factory.怎么解决

became_an_icer

test代码：
program automatic test;
    import uvm_pkg::*;
    `include "uvm_macros.svh"
    initial begin
        run_test("my_test");
    end
endprogram


my_test代码：
class my_test extends uvm_test;

    `uvm_component_utils(my_test);
    my_env m_env;
    function new(string name = "my_test", uvm_component parent=null);
        super.new(name, parent);
    endfunction

    virtual function void build_phase(uvm_phase phase);
       super.build_phase(phase);
        m_env=my_env::type_id::create("m_env",this);
        uvm_config_db#(uvm_object_wrapper)::set(this, "*.m_seqr.run_phase", "default_sequence", my_sequence::get_type());
    endfunction: build_phase
endclass


vlog和vsim都成功，但是run后就会出现这样的结果：
UVM_WARNING @ 0: reporter [BDTYP] Cannot create a component of type 'my_test' because it is not registered with the factory.
# UVM_FATAL @ 0: reporter [INVTST] Requested test from call to run_test(my_test) not found.

我的my_test不是已经注册到uvm_component_util中了吗，为什么还会报错？？？？求大神解答啊。。。弄了好半天还没解决

became_an_icer

用vcs后也一样

became_an_icer

这是我的questasim的命令行，有没有错误
cd I:/vs_code/testbeach
vlib work
set UVM_HOME K:/questasim/questasim/verilog_src/uvm-1.1d   
set WORK_HOME I:/vs_code/testbeach
vlog +incdir+$UVM_HOME/src  -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPF $UVM_HOME/src/uvm_pkg.sv  $WORK_HOME/test.sv
vsim  -c -sv_lib K:/questasim/questasim/uvm-1.1d/win64/uvm_dpi work.test    -voptargs=+acc

became_an_icer

这是我的vcs的命令行，有没有错误   

vcs -sverilog -debug_pp -LDFLAGS -rdynamic \
-P ${VERDI_HOME}/share/PLI/VCS/LINUX64/novas.tab \
${VERDI_HOME}/share/PLI/VCS/LINUX64/pli.a \
${UVM_HOME}/src/dpi/uvm_dpi.cc -CFLAGS -DVCS \
+incdir+${UVM_HOME}/src   \
${UVM_HOME}/src/uvm_pkg.sv  test.sv \
-R  +UVM_TESTNAME=my_test   +vcs+lic+wait  \
-timescale=1ns/1ns -l com.log

sfc19910705

漏了$WORK_HOME/my_test.sv

eaglezhang01

是不是真如楼上所说my_test这个class根本没编译进去

became_an_icer

sfc19910705 发表于 2021-11-16 09:42
漏了$WORK_HOME/my_test.sv

在vcs中添加了这个后 出现了这种结果Error-[SE] Syntax error
  Following verilog source has syntax error :
  "my_test.sv", 1: token is 'uvm_test'
  class my_test extends uvm_test;

sfc19910705

became_an_icer 发表于 2021-11-17 14:42
在vcs中添加了这个后 出现了这种结果Error-[SE] Syntax error
  Following verilog source has syntax err ...

淡定，vcs编译命令里面是不是少了$UVM_HOME/src/uvm_pkg.sv

became_an_icer

sfc19910705 发表于 2021-11-17 17:13
淡定，vcs编译命令里面是不是少了$UVM_HOME/src/uvm_pkg.sv

哈哈，有的，编译了
vcs -sverilog -debug_pp -LDFLAGS -rdynamic \
-P ${VERDI_HOME}/share/PLI/VCS/LINUX64/novas.tab \
${VERDI_HOME}/share/PLI/VCS/LINUX64/pli.a \
${UVM_HOME}/src/dpi/uvm_dpi.cc -CFLAGS -DVCS \
+incdir+${UVM_HOME}/src   \
${UVM_HOME}/src/uvm_pkg.sv  test.sv  my_test.sv \
-R  +UVM_TESTNAME=my_test   +vcs+lic+wait  \
-timescale=1ns/1ns -l com.log

sfc19910705

became_an_icer 发表于 2021-11-17 20:37
哈哈，有的，编译了
vcs -sverilog -debug_pp -LDFLAGS -rdynamic \
-P ${VERDI_HOME}/share/PLI/VCS/L ...

    import uvm_pkg::*;
    `include "uvm_macros.svh"
program automatic test;
    initial begin
        run_test("my_test");
    end
endprogram