DC综合问题

Gecy1226

-----------------verilog code---------------------
module Add1(a, b, out, Sys_clk);

input a, b;
output out;
reg out;
input Sys_clk;

always @(posedge Sys_clk)
        out <= a+b;

endmodule


-----------------constrain code---------------------
start_gui
#setup the libs
set target_library ./libs/typical.db
set symbol_library ./libs/tsmc090.sdb
set link_library {./libs/tsmc090.sdb ./libs/typical.db}

#read the design
analyze -format verilog {./rtl/Add1.v}
elaborate Add1

#set current design and link
current_design Add1
link
uniquify
check_design

#set clk
create_clock -period 4 -waveform {0 2} -name Sys_clk [get_ports Sys_clk]
set_ideal_network {Sys_clk}
set_dont_touch_network [get_clocks Sys_clk]

#set input output delay
set_input_delay -max 0.2 -clock Sys_clk [all_inputs]
set_output_delay -max 0.2 -clock Sys_clk [all_outputs]

#compile the design
compile -exact_map

综合结果

report_timing 结果不对啊。约束哪里出问题了？

Gecy1226

up, 求大佬点拨一下

Gecy1226

up....

碰巧80后

这个可以学习一下

七点班车

set link_library {./libs/tsmc090.sdb ./libs/typical.db}改成set link_library {*  ./libs/tsmc090.sdb ./libs/typical.db}，你可以看看log，应该是有warning说unresolved reference

Gecy1226

问题出在库没有吃成功。