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[求助] 关于vivado和modelism的关联问题

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发表于 2016-10-24 15:27:42 | 显示全部楼层 |阅读模式

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在编译库的时候,3个vhdl的库老是有error,不知道是什么问题,下面是编译的过程:跪求各位大大帮忙。。。。
compile_simlib -language all -dir {C:/xilinx_sim_lib} -simulator modelsim -simulator_exec_path {C:/modeltech64_10.4/win64} -library all -family  all
Compiling libraries for 'modelsim' in 'C:\xilinx_sim_lib'
** Warning: (vlib-34) Library already exists at "C:\xilinx_sim_lib/secureip".

Library verilog.secureip:verilog.axi_bfm will not be compiled, because precompiled library info is up to date.
** Warning: (vlib-34) Library already exists at "C:\xilinx_sim_lib/secureip".

Library verilog.secureip will not be compiled, because precompiled library info is up to date.
compile_simlib[verilog.secureip]: 0 error(s), 0 warning(s), 25.00 % complete



Library vhdl.unisim will be compiled, because precompiled library info is stale.
** Warning: (vlib-34) Library already exists at "C:\xilinx_sim_lib/unisim".
--> Compiling 'vhdl.unisim' library...
    > Source Library = 'C:\Xilinx\Vivado\2014.4\data/vhdl/src/unisims'
    > Compiled Path  = 'C:\xilinx_sim_lib/unisim'
    > Log File       = 'C:\xilinx_sim_lib/unisim/.cxl.vhdl.unisim.unisim.nt64.log'

Library vhdl.unisim:vhdl.unimacro will be compiled, because precompiled library info is stale.
** Warning: (vlib-34) Library already exists at "C:\xilinx_sim_lib/unimacro".
--> Compiling 'vhdl.unisim:vhdl.unimacro' library...
    > Source Library = 'C:\Xilinx\Vivado\2014.4\data/vhdl/src/unimacro'
    > Compiled Path  = 'C:\xilinx_sim_lib/unimacro'
    > Log File       = 'C:\xilinx_sim_lib/unimacro/.cxl.vhdl.unimacro.unimacro.nt64.log'
compile_simlib[vhdl.unisim:vhdl.unimacro]: 1 error(s), 0 warning(s)

INFO: Please refer to the messages between 'BEGIN_COMPILATION_MESSAGES(modelsim:vhdl:unimacro)' and 'END_COMPILATION_MESSAGES(modelsim:vhdl:unimacro)' in the log file compile_simlib.log for details of compilation error(s).


Library vhdl.unisim:vhdl.unifast will be compiled, because precompiled library info is stale.
** Warning: (vlib-34) Library already exists at "C:\xilinx_sim_lib/unifast".
--> Compiling 'vhdl.unisim:vhdl.unifast' library...
    > Source Library = 'C:\Xilinx\Vivado\2014.4\data/vhdl/src/unifast'
    > Compiled Path  = 'C:\xilinx_sim_lib/unifast'
    > Log File       = 'C:\xilinx_sim_lib/unifast/.cxl.vhdl.unifast.unifast.nt64.log'
compile_simlib[vhdl.unisim:vhdl.unifast]: 1 error(s), 0 warning(s)

INFO: Please refer to the messages between 'BEGIN_COMPILATION_MESSAGES(modelsim:vhdl:unifast)' and 'END_COMPILATION_MESSAGES(modelsim:vhdl:unifast)' in the log file compile_simlib.log for details of compilation error(s).

compile_simlib[vhdl.unisim]: 3 error(s), 0 warning(s), 50.00 % complete


Please refer to the messages between 'BEGIN_COMPILATION_MESSAGES(modelsim:vhdl:unisim)' and 'END_COMPILATION_MESSAGES(modelsim:vhdl:unisim)' in the log file compile_simlib.log for details of compilation error(s).

** Warning: (vlib-34) Library already exists at "C:\xilinx_sim_lib/unimacro_ver".

Library verilog.unisim:verilog.unimacro will not be compiled, because precompiled library info is up to date.
** Warning: (vlib-34) Library already exists at "C:\xilinx_sim_lib/unifast_ver".

Library verilog.unisim:verilog.unifast will not be compiled, because precompiled library info is up to date.
** Warning: (vlib-34) Library already exists at "C:\xilinx_sim_lib/unisims_ver".

Library verilog.unisim will not be compiled, because precompiled library info is up to date.
compile_simlib[verilog.unisim]: 0 error(s), 0 warning(s), 75.00 % complete


** Warning: (vlib-34) Library already exists at "C:\xilinx_sim_lib/simprims_ver".

Library verilog.simprim will not be compiled, because precompiled library info is up to date.
compile_simlib[verilog.simprim]: 0 error(s), 0 warning(s), 100.00 % complete


Copying setup file 'modelsim.ini' to 'C:\xilinx_sim_lib/modelsim.ini' ...

****************************************************************************
*                          COMPILATION SUMMARY                             *
*                                                                          *
*  Simulator used: modelsim                                                *
*  Compiled on: Mon Oct 24 15:27:04 2016                                   *
*                                                                          *
****************************************************************************
*  Library        | Language | Mapped Library Name | Error(s) | Warning(s) *
*--------------------------------------------------------------------------*
*  unisim         | vhdl     | unisim              | 3        | 0          *
*--------------------------------------------------------------------------*
*  unimacro       | vhdl     | unimacro            | 1        | 0          *
*--------------------------------------------------------------------------*
*  unifast        | vhdl     | unifast             | 1        | 0          *
*--------------------------------------------------------------------------*

ERROR: [Vivado 12-3591] compile_simlib failed to compile for modelsim with 5 errors.
compile_simlib: Time (s): cpu = 00:00:01 ; elapsed = 00:00:25 . Memory (MB): peak = 800.156 ; gain = 0.000
ERROR: [Common 17-39] 'compile_simlib' failed due to earlier errors.
发表于 2017-9-7 11:25:16 | 显示全部楼层
楼主解决问题了吗?同样遇到了  vivado2015.4 modelsim 10.4
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发表于 2017-9-7 11:34:49 | 显示全部楼层
在log文件中找到的错误提示
BEGIN_COMPILATION_MESSAGES(modelsim:vhdl:unifast)
Model Technology ModelSim SE-64 vcom 10.4 Compiler 2014.12 Dec  3 2014
Start time: 11:15:58 on Sep 07,2017
vcom -source -93 -novopt -64 -work unifast -f D:\modeltech\vivado2015_lib/unifast/.cxl.vhdl.unifast.unifast.nt64.cmf
** Error: Library std not found.
** Error: VHDL Compiler exiting
End time: 11:15:58 on Sep 07,2017, Elapsed time: 0:00:00
Errors: 2, Warnings: 0

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