ET创芯网论坛(EETOP)

找回密码

  登录   注册  

搜索
《ADI参考电路》限时下载!奖励300信元!
查看: 694|回复: 0

[招聘] [AMD社招] SMTS ASIC Design Verification Engineer

[复制链接]
发表于 2016-10-21 16:46:08 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有帐号?注册

x
SMTS ASIC Design Verification Engineer
Job Location: Beijing/Shanghai

Job description:
We are currently looking for engineer who will be responsible for design verification of cutting edge GPU projects. Qualified candidate will participate in and lead SoC level function verification domains including:
1.        SoC DV testbench and infrastructure development and maintenance
2.        Create and execute SoC testplan including data-path and interrupt, virtualization, security, power management, etc.
3.        Implement directed and random test cases in C++/SV, as well as checkers and assertions
4.        Support integration and qualification of all the IPs for SoC
5.        Help to improve DV environment building flow

Requirement:
-   MS with 7+ or BS with 9+ years’ experience in ASIC/SoC design verification
-   DV lead experience is a must
-   Hand-on experience in all domains of complex ASIC DV flow from plan to coverage, both
-   Knowledgeable in C++ & SV development, familiar with scripting languages like Ruby/Perl/Makefile…
-   Strong problem solving and communication skills
-   Knowledge on computer architecture and PCIe devices is highly preferred
-   Good knowledge on verification methodologies like UVM is a big plus
-   Experience in power-aware verification is an asset
您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐上一条 /1 下一条

关于我们|联系我们|ET创芯网 ( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2019-10-19 02:41 , Processed in 0.065990 second(s), 13 queries , Gzip On, Redis On.

Powered by Discuz! X3.4

© 2001-2017 Comsenz Inc.

快速回复 返回顶部 返回列表