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[原创] Xilinx ISE官方IP可以解密源码了

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发表于 2014-12-29 09:43:25 | 显示全部楼层 |阅读模式

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ISE带的IP已经可以解密源码了,有需要的可以联系我哦
发表于 2015-6-17 17:51:05 | 显示全部楼层
我有这个需求。怎么联系你,留个联系方式?谢谢!
发表于 2015-8-14 14:19:09 | 显示全部楼层
你好,报个价格
发表于 2015-8-21 10:41:39 | 显示全部楼层
报个价啊
 楼主| 发表于 2015-8-21 17:52:13 | 显示全部楼层
有需要+Q:5523785
发表于 2015-10-11 18:47:14 | 显示全部楼层
这个很容易还来卖钱。 基本原理是在libisl_iostream找到RSA的私钥解出AES密钥,就可以用这个解出内容。
调用openssl的crypt库编程不超过100行。 看我的vivado can_V5_0.vhd这个文件如下

---------------------------------------------------
-- (c) Copyright 2007 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------------------
-- Generated by XCC2VHDL IP-XACT conversion v1.2

library ieee;
use ieee.std_logic_1164.all;

library can_v5_0;
use can_v5_0.all;

entity can_v5_0 is
        generic (
                c_can_rx_dpth : integer := 64;
                c_can_tx_dpth : integer := 64;
                c_can_num_acf : integer := 4;
                c_c2s_mtbf_stages : integer := 2;
                c_s2c_mtbf_stages : integer := 2;
                c_s_axi_addr_width : integer := 8;
                c_s_axi_data_width : integer := 32;
                c_family : string := "virtex7"
        );
        port (
                can_clk : in std_logic := '0';
                can_phy_rx : in std_logic := '0';
                can_phy_tx : out std_logic;
                ip2bus_intrevent : out std_logic;
                s_axi_aclk : in std_logic := '0';
                s_axi_aresetn : in std_logic := '0';
                --s_axi_awaddr : in std_logic_vector(c_s_axi_addr_width - 1 downto 0) := (others => '0');
                s_axi_awaddr : in std_logic_vector(8 - 1 downto 0) := (others => '0');
                s_axi_awvalid : in std_logic := '0';
                s_axi_awready : out std_logic;
                --s_axi_wdata : in std_logic_vector(c_s_axi_data_width - 1 downto 0) := (others => '0');
                s_axi_wdata : in std_logic_vector(32 - 1 downto 0) := (others => '0');
                --s_axi_wstrb : in std_logic_vector((c_s_axi_data_width / 8 ) - 1 downto 0) := (others => '0');
                s_axi_wstrb : in std_logic_vector((32 / 8 ) - 1 downto 0) := (others => '0');
                s_axi_wvalid : in std_logic := '0';
                s_axi_wready : out std_logic;
                s_axi_bresp : out std_logic_vector(1 downto 0);
                s_axi_bvalid : out std_logic;
                s_axi_bready : in std_logic := '0';
                --s_axi_araddr : in std_logic_vector(c_s_axi_addr_width - 1 downto 0) := (others => '0');
                s_axi_araddr : in std_logic_vector(8 - 1 downto 0) := (others => '0');
                s_axi_arvalid : in std_logic := '0';
                s_axi_arready : out std_logic;
                --s_axi_rdata : out std_logic_vector(c_s_axi_data_width - 1 downto 0);
                s_axi_rdata : out std_logic_vector(32 - 1 downto 0);
                s_axi_rresp : out std_logic_vector(1 downto 0);
                s_axi_rvalid : out std_logic;
                s_axi_rready : in std_logic := '0'
        );
end entity can_v5_0;

architecture xilinx of can_v5_0 is

attribute DowngradeIPIdentifiedWarnings: string;

attribute DowngradeIPIdentifiedWarnings of xilinx : architecture is "yes";

        constant eval_tic_ps : integer := 10000;
begin
        core_options : if true generate
                begin cantop_i : entity can_top
                generic map (
                        c_can_rx_dpth => c_can_rx_dpth,
                        c_can_tx_dpth => c_can_tx_dpth,
                        c_can_num_acf => c_can_num_acf,
                        c_c2s_mtbf_stages => c_c2s_mtbf_stages,
                        c_s2c_mtbf_stages => c_s2c_mtbf_stages,
                        c_s_axi_addr_width => c_s_axi_addr_width,
                        c_s_axi_data_width => c_s_axi_data_width,
                        c_family => c_family
                )
                port map (
                        can_clk => can_clk,
                        can_phy_rx => can_phy_rx,
                        can_phy_tx => can_phy_tx,
                        ip2bus_intrevent => ip2bus_intrevent,
                        s_axi_aclk => s_axi_aclk,
                        s_axi_aresetn => s_axi_aresetn,
                        s_axi_awaddr => s_axi_awaddr,
                        s_axi_awvalid => s_axi_awvalid,
                        s_axi_awready => s_axi_awready,
                        s_axi_wdata => s_axi_wdata,
                        s_axi_wstrb => s_axi_wstrb,
                        s_axi_wvalid => s_axi_wvalid,
                        s_axi_wready => s_axi_wready,
                        s_axi_bresp => s_axi_bresp,
                        s_axi_bvalid => s_axi_bvalid,
                        s_axi_bready => s_axi_bready,
                        s_axi_araddr => s_axi_araddr,
                        s_axi_arvalid => s_axi_arvalid,
                        s_axi_arready => s_axi_arready,
                        s_axi_rdata => s_axi_rdata,
                        s_axi_rresp => s_axi_rresp,
                        s_axi_rvalid => s_axi_rvalid,
                        s_axi_rready => s_axi_rready
                );
               
        end generate core_options;
       
end architecture xilinx;
 楼主| 发表于 2015-10-11 23:42:59 | 显示全部楼层
这个是ise的ip和vivado的不一样
发表于 2015-10-12 12:47:22 | 显示全部楼层
由于libisl_iostream.dll加了他们自己的壳,需要先脱壳,后看到他们也是用的openssl库。 不想脱壳可以用Cadence,mentor,synopsys的程序找私钥,一样的过程可以得到 AES密钥
发表于 2015-10-20 23:18:44 | 显示全部楼层
这个横好的建议!!!
发表于 2015-10-21 15:58:52 | 显示全部楼层
回复 8# doomsten


    请问,用什么工具脱壳呢?
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