每日一奖----20140506

damonzhao

看到之前szp9912 的帖子http://bbs.eetop.cn/thread-308503-1-1.html 后来也没有下文了，我来做个推手，把活动进行下去。希望大家踊跃回答，积极讨论，回答无深浅，不必面面俱到，只为讨论。悬赏给问题回答的相对全面的人，大家可以有异议，只要共同进步就好。

Ok，let's go！

Q1. Explain the flow of physical design and inputs and outputs for each step in flow.

jinwei91

Have a try.

Flow with ICC: initial, floorplan, place&place_opt, cts&cts_opt, route&route_opt, finish.
inputs & outputs for each step:

1) initial:
input: synthesis data(gate-level netlist, constraint files, etc.) and physical data(standard cell/memory/io/ip library milkyway/db directories, techfile, TLU+ files, antenna file from foundry, etc.)
output: check_timing & check_design report;

2) floorplan:
input: floorplan of your design by write_floorplan from your floorplan design, include tapcell/endcap/switchcell location, powerplan, pin plan, global placement/routing blockage settings etc.

3)place&place_opt:
input: constraint for placement. e.g. : dont_touch/dont_use cells settings, keepout settings, group path settings, gate checking settings, etc.

4)cts&cts_opt:
input: constraint for cts. e.g.: clock transition, cts cells settings, clock metal layer settings, target skew settings, clock derate settings, none default rule settings, special cts constraints for memory and ip, etc.
output: clock timing check report, riming report after cts_opt, etc.

5)route& route_opt:
input: constraint for routing. e.g.: redundant via stttings, max net length, x-talk settings, widen wire settings, etc.
output: timing report for route_opt.

6)finish:
input: fill/dcap insertion scripts, gds layer map, etc.
output: design report(report_design, qor, power, etc.), timing report, clock tree, clock timing, netlist(for STA and for LVS), gds/oa, DEF, FRAM etc.

pandafeeder

顶一个，好问题，期待好答案，在下小丑就不跳梁了...

crafty1120

坐等大牛出现~

damonzhao

回复 2# pandafeeder


   重在参与，不用不好意思，有钱赚哦！

damonzhao

回复 3# crafty1120


   给我你的答案，不用等别人，你就是大牛！

xwwwjy

楼主能给个解答吗，菜鸟想学习下

igooo

回复 6# jinwei91


   

KevinIC

回复 6# jinwei91

Good Summary.

One thing to add.
In your initial phase, if synthesis by DCG flow, the input data should include DEF file of cells' location.
Also, there should be scan def file as well if have DFT.

nw885566

1)、初始化设置
     包括逻辑库的设置、物理库的设置和TLUPlus相关文件的设置等；
2）芯片的设计规划（Design Planning）
     A、布图规划（floorplan）
     B、电源规划（Powerplan）
3）芯片的布局（Placement）
4）芯片的布局优化（Placement_opt）
5）时钟数的逻辑综合（clock_cts）
6）时钟数的物理综合（clock-psyn）
7）时钟数的布线（clock-route）
8）时钟数的布线（routing）
9)时钟数的布线优化（routing_optimization）
10）芯片的可制造性设计（Design for manufacturing）(inserting tap/filler cells)