关于xilinx MIG核使用

598135385 · 发表于 2017-8-13 14:59:48

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本人用xilinx MIG核自带例程仿真DDR3程序可以实现数据读写，然后删除例程中traffic_gen_top模块，改成自己写的读写状态机，并把例程中的的ddr3_model连接到我的工程，MIG核初始化完成后，写入数据写到第16个数据时，MIG核的app_wdf_rdy信号就一直拉低，写不进去数。有没有仿真过的大神指点一下哪里有问题

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:44:13 08/11/2017
// Design Name:
// Module Name: my_ddr3_ctrl
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module my_ddr3_ctrl(
input wire clk,
input wire rst,
input wire memc_init_done,
input wire memc_cmd_full,
output wire memc_cmd_en,
output wire [2:0] memc_cmd_instr,
output wire [31:0] memc_cmd_addr,
output wire memc_wr_en,
output wire memc_wr_end,
output wire [31:0] memc_wr_mask,
output wire [63:0] memc_wr_data,
input wire memc_wr_full,
input wire [63:0] memc_rd_data,
input wire memc_rd_data_valid,
//fifo接口
input wire [63:0] Din,
input wire Din_valid,
input wire IMG_OK,
output reg Rd_fifo,
output wire ddr3_rd_clk,
output wire Dout_valid,
output wire ddr3_wr_clk,
output reg ddr3_read_finish,
output wire [63:0] Dout
);
parameter BASE_ADDR = 32'h0000_0000;
parameter READ_CMD = 3'b000,
WRITE_CMD = 3'b001;
parameter IMG_SIZE = 15'd16384;
//写入DDR3操作
parameter WRITE_IDLE = 4'b0001,
WRITE_READY = 4'b0010,
WRITE_OPT = 4'b0100,
WRITE_END = 4'b1000;
parameter READ_IDLE = 4'b0001,
READ_READY = 4'b0010,
READ_OPT = 4'b0100,
READ_END = 4'b1000;
reg [3:0] wr_cstate,wr_nstate;
reg [3:0] rd_cstate,rd_nstate;
reg [14:0] wr_data_cnt,rd_data_cnt;
reg [26:0] wr_addr,rd_addr;
reg wr_ddr3,rd_ddr3;
reg ddr3_wr_busy,ddr3_rd_busy;
reg wr_finish;
assign memc_cmd_instr = (wr_ddr3) ? WRITE_CMD : ((rd_ddr3) ? READ_CMD : 3'b111);
assign memc_cmd_en = wr_ddr3 || rd_ddr3;
assign memc_cmd_addr = (wr_ddr3) ? wr_addr : rd_addr;
assign ddr3_rd_clk = clk;
assign ddr3_wr_clk = clk;
assign memc_wr_data= Din;
assign memc_wr_en = Din_valid;
assign memc_wr_end = Din_valid;
assign Dout = memc_rd_data;
assign Dout_valid = memc_rd_data_valid;
always @ (posedge clk or negedge rst) begin
if(~rst) begin
wr_cstate <= WRITE_IDLE;
end
else begin
wr_cstate <= wr_nstate;
end
end
always @ ( * ) begin
case(wr_cstate)
WRITE_IDLE : begin
if(memc_init_done) wr_nstate = WRITE_READY;
else wr_nstate = WRITE_IDLE;
end
WRITE_READY : begin
if(~memc_wr_full && ~memc_cmd_full && IMG_OK && ~ddr3_rd_busy)
wr_nstate = WRITE_OPT;
else wr_nstate = WRITE_READY;
end
WRITE_OPT : begin
if(memc_wr_full || memc_cmd_full || ddr3_rd_busy)
wr_nstate = WRITE_READY;
else if(wr_data_cnt < IMG_SIZE) wr_nstate = WRITE_OPT;
else wr_nstate = WRITE_END;
end
WRITE_END : begin
wr_nstate = WRITE_END;
end
default : wr_nstate = WRITE_IDLE;
endcase
end
always @ (posedge clk or negedge rst) begin
if(~rst) begin
wr_data_cnt <= 0;
wr_addr <= BASE_ADDR;
Rd_fifo <= 0;
wr_ddr3 <= 0;
wr_finish <= 0;
ddr3_wr_busy <= 0;
end
else begin
case(wr_nstate)
WRITE_IDLE : begin
wr_data_cnt <= 0;
wr_addr <= BASE_ADDR;
Rd_fifo <= 0;
wr_ddr3 <= 0;
wr_finish <= 0;
ddr3_wr_busy <= 0;
end
WRITE_READY : begin
wr_data_cnt <= wr_data_cnt;
wr_addr <= wr_addr;
Rd_fifo <= 0;
wr_ddr3 <= 0;
wr_finish <= 0;
ddr3_wr_busy <= 0;
end
WRITE_OPT : begin
wr_data_cnt <= wr_data_cnt + 1;
wr_addr <= wr_addr + 8; //app端一次写BL=8个
Rd_fifo <= 1;
wr_ddr3 <= 1;
wr_finish <= 0;
ddr3_wr_busy <= 1;
end
WRITE_END : begin
wr_data_cnt <= 0 ;
wr_addr <= BASE_ADDR;
Rd_fifo <= 0;
wr_ddr3 <= 0;
wr_finish <= 1;
ddr3_wr_busy <= 0;
end
default : begin
wr_data_cnt <= 0 ;
wr_addr <= BASE_ADDR;
Rd_fifo <= 0;
wr_ddr3 <= 0;
wr_finish <= 0;
ddr3_wr_busy <= 0;
end
endcase
end
end
//读取ddr数据
always @ (posedge clk or negedge rst) begin
if(~rst) begin
rd_cstate <= READ_IDLE;
end
else begin
rd_cstate <= rd_nstate;
end
end
always @ ( * ) begin
case(rd_cstate)
READ_IDLE : begin
if(memc_init_done) rd_nstate = READ_READY;
else rd_nstate = READ_IDLE;
end
READ_READY : begin
if(~memc_cmd_full && wr_finish && ~ddr3_wr_busy)
rd_nstate = READ_OPT;
else rd_nstate = READ_READY;
end
READ_OPT : begin
if(rd_data_cnt < IMG_SIZE) rd_nstate = READ_OPT;
else rd_nstate = READ_END;
end
READ_END : begin
rd_nstate = READ_END;
end
default : rd_nstate = READ_IDLE;
endcase
end
always @ (posedge clk or negedge rst) begin
if(~rst) begin
rd_addr <= 0;
rd_ddr3 <= 0;
rd_data_cnt <= 0;
ddr3_rd_busy <= 0;
ddr3_read_finish<= 0;
end
else begin
case(rd_nstate)
READ_IDLE : begin
rd_addr <= BASE_ADDR;
rd_ddr3 <= 0;
rd_data_cnt <= 0;
ddr3_rd_busy <= 0;
ddr3_read_finish <= 0;
end
READ_READY : begin
rd_addr <= rd_addr;
rd_ddr3 <= 0;
rd_data_cnt <= rd_data_cnt;
ddr3_rd_busy <= 0;
ddr3_read_finish <= 0;
end
READ_OPT : begin
rd_addr <= rd_addr +8;
rd_ddr3 <= 1;
rd_data_cnt <= rd_data_cnt + 1;
ddr3_rd_busy <= 1;
ddr3_read_finish <= 0;
end
READ_END : begin
rd_addr <= BASE_ADDR;
rd_ddr3 <= 0;
rd_data_cnt <= 0;
ddr3_rd_busy <= 0;
ddr3_read_finish <= 1;
end
default : begin
rd_addr <= BASE_ADDR;
rd_ddr3 <= 0;
rd_data_cnt <= 0;
ddr3_rd_busy <= 0;
ddr3_read_finish <= 0;
end
endcase
end
end
endmodule

复制代码

598135385 · 发表于 2017-8-15 13:04:11

从仿真图上看ddr_dp一直出的数据跟我写的数据不一样

[求助] 关于xilinx MIG核使用

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