高价悬赏（几百到几万）后端设计案例，用于EDA软件测试！

金海林

需要如下文件（要求文件间的数据是配套的）1.Hierarchical gate_level verilog netlist files (multiple modules) *.v

2.timing constraints file( Synopsys Design Constraint file) *.sdc

3.hierarchical interconnect RC spef files ( multiple blocks ) *.spef

4.Liberty timing library files (including delay, transition, must have power table) *.lib

5.LEF files ( including lef technology file) *.lef

6.hierarchical DEF files ( must have POWER and GROUND nets) *.def

7.VDD and GND pad location file

8.Interconnect Technology File ( ITF file)  *.itf  
this file is from foundry such as TSMC 28nm

9. gate-level verilog simulation (value change dump) VCD file  *.vcd


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