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Efficiency Enhancement Techniques for CMOS RF
Power Amplifiers,2006, Naratip Wongkome Paul R. Gray,University of California, Berkeley
Chapter 1: Introduction 1
1.1 Motivation 1
1.2 Power Amplifier in Modern Wireless Applications 3
1.3 Research Goals 4
1.4 Thesis Organization 7
Chapter 2: RF Power Amplifier Fundamentals 8
2.1 Power Amplifier Basics 9
2.2 Power Efficiency 10
2.3 Linearity 13
2.3.1 AM-to-AM and AM-to-PM Characteristic 15
2.3.2 Spectral Mask 16
2.3.3 Adjacent Channel Leakage Ratio 17
2.3.4 Error Vector Magnitude 18
2.4 Typical PA circuit 19
2.5 Power Amplifier Classes 21
2.5.1 Class A Amplifier 21
2.5.2 Class AB,B, and C Amplifiers 24
2.5.3 Class D Amplifier 27
2.5.4 Class E Amplifier 29
2.5.5 Class F Amplifier 30
Chapter 3: Power Amplifier Enhance Techniques 34
3.1 PA Enhancement Techniques 35
3.2 Efficiency Enhancement Techniques 36
3.2.1 Doherty Amplifier 37
3.2.2 Power Supply Variation 40
3.2.3 Bias Adaptation
3.3 Linearization Techniques 43
3.3.1 Feedback 43
3.3.2 Predistortion 46
3.3.3 Envelope Elimination and Restoration (EER) 47
3.3.4 Chireix’s Outphasing 48
Chapter 4: Doherty Amplifier 51
4.1 Doherty Amplifier Block Diagram 52
4.2 Passive Impedance Inverter (Z
) 53
inv
4.3 Doherty Amplifier Operation 54
4.4 Linear Doherty Amplifier 63
4.5 Effect of Lossy Z Network 67
inv
4.6 Tuning of Z Network 70
inv
4.7 Nonlinear Doherty Amplifier 72
4.8 Effect of Load Variation 75
4.9 Multi-stage Doherty Amplifier 77
Chapter 5: Linear Amplifier Design 79
5.1 Linear Output Stage Design 81
5.2 Linear Output Stage with Cascode Transistor 95
5.3 Driver Stage Design 97
5.4 Capacitive Neutralization Technique
5.5 Interstage Matching 105
5.6 Output Matching Network 107
Chapter 6: CMOS Protype and Experimental Results 114
6.1 Doherty Amplifier Building Blocks 114
6.1.1 Polyphase Circuit 115
6.1.2 Main and Auxiliary Amplifiers 117
6.1.2.1 Output Stage 118
6.1.2.2 Interstage Matching 121
ii
6.1.2.3 Predriver and Driver 123
6.1.3 Output Matching Network 124
6.1.4 Impedance Inverter Network 127
6.1.5 Switched Capacitor Array 129
6.2 Overall Simulation Results 134
6.3 CMOS Prototype 137
6.4 Experimental Results 138
Chapter 7: Conclusion 142 |
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