GCLK不够用怎么办

raojp · 发表于 2018-3-7 08:25:15

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各位同学，请教个问题：使用Xilinx Spartan6器件，需要接入24个100M网口，接口为MII，Spartan6只有16个GCLK，这就意味着还有8个MII接口的rxc无法接入全局时钟，对应的逻辑会面临因为clock delay不一致带来的建立保持时间问题，大家有什么解决办法吗？提前拜谢了

raojp · 发表于 2018-3-7 09:13:02

知道的朋友帮忙解答一下哦

raojp · 发表于 2018-3-7 13:34:32

下面是没有经BUFG占用global clock tree的MII 时钟的timing report:
mii_clk到frame_info_wen和frame_info_in[26:0]的delay差值最大为3.14ns，很容易导致写入的信息不对。有什么办法约束吗？

Net "mac5_rxc_IBUF":
9.406ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram.CLKAWRCLK", site.pin "RAMB8_X3Y39.CLKAWRCLK"
7.698ns - comp.pin "inst_mii_5/inst_encap/inst_frame_buf/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram.CLKA", site.pin "RAMB16_X3Y50.CLKA"
7.936ns - comp.pin "inst_mii_5/inst_encap/inst_frame_buf/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram.CLKA", site.pin "RAMB16_X3Y48.CLKA"
7.807ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/temp_addr_rec_pack<3>.CLK", site.pin "SLICE_X50Y107.CLK"
7.789ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/temp_addr_rec_pack<7>.CLK", site.pin "SLICE_X50Y108.CLK"
7.605ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/temp_addr_rec_pack<11>.CLK", site.pin "SLICE_X50Y109.CLK"
7.258ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/rec_count_nibble<3>.CLK", site.pin "SLICE_X46Y100.CLK"
7.074ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/rec_count_nibble<7>.CLK", site.pin "SLICE_X46Y101.CLK"
8.372ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/rec_count_nibble<11>.CLK", site.pin "SLICE_X46Y102.CLK"
8.919ns - comp.pin "inst_mii_5/inst_encap/frame_len_byte<3>.CLK", site.pin "SLICE_X52Y83.CLK"
8.904ns - comp.pin "inst_mii_5/inst_encap/frame_len_byte<7>.CLK", site.pin "SLICE_X52Y84.CLK"
8.708ns - comp.pin "inst_mii_5/inst_encap/frame_len_byte<10>.CLK", site.pin "SLICE_X52Y85.CLK"
driver - comp.pin "mac5_rxc.I", site.pin "F8.I"
2.963ns - comp.pin "inst_encap_fiber_port5/mac_rxdv_1d.CLK0", site.pin "ILOGIC_X3Y116.CLK0"
2.776ns - comp.pin "inst_encap_fiber_port5/mac_rxerr_1d.CLK0", site.pin "ILOGIC_X3Y118.CLK0"
3.413ns - comp.pin "inst_encap_fiber_port5/mac_rxd_1d<0>.CLK0", site.pin "ILOGIC_X2Y117.CLK0"
3.149ns - comp.pin "inst_encap_fiber_port5/mac_rxd_1d<1>.CLK0", site.pin "ILOGIC_X2Y118.CLK0"
3.149ns - comp.pin "inst_encap_fiber_port5/mac_rxd_1d<2>.CLK0", site.pin "ILOGIC_X2Y119.CLK0"
2.776ns - comp.pin "inst_encap_fiber_port5/mac_rxd_1d<3>.CLK0", site.pin "ILOGIC_X3Y119.CLK0"
4.174ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<0>.CLK", site.pin "SLICE_X0Y100.CLK"
3.983ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2.CLK", site.pin "SLICE_X0Y102.CLK"
4.146ns - comp.pin "inst_encap_fiber_port2/rec_mac_pack_z_inst/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/Mmux_comp1_GND_222_o_MUX_12_o13.CLK", site.pin "SLICE_X0Y103.CLK"
3.488ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>.CLK", site.pin "SLICE_X0Y110.CLK"
3.535ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i.CLK", site.pin "SLICE_X4Y110.CLK"
3.120ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<3>.CLK", site.pin "SLICE_X6Y110.CLK"
3.301ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<7>.CLK", site.pin "SLICE_X7Y108.CLK"
3.300ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<3>.CLK", site.pin "SLICE_X7Y109.CLK"
3.120ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<7>.CLK", site.pin "SLICE_X7Y110.CLK"
3.591ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>.CLK", site.pin "SLICE_X9Y107.CLK"
3.771ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<5>.CLK", site.pin "SLICE_X11Y110.CLK"
3.873ns - comp.pin "inst_encap_fiber_port5/mac_rxerr_2d.CLK", site.pin "SLICE_X12Y107.CLK"
3.695ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>.CLK", site.pin "SLICE_X12Y108.CLK"
4.133ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<5>.CLK", site.pin "SLICE_X13Y103.CLK"
3.695ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>.CLK", site.pin "SLICE_X13Y108.CLK"
6.224ns - comp.pin "inst_encap_fiber_port5/mac_rxd_2d<3>.CLK", site.pin "SLICE_X23Y107.CLK"
6.056ns - comp.pin "inst_mii_5/inst_encap/frame_info_wen.CLK", site.pin "SLICE_X27Y101.CLK"
5.753ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/vld_pkt_recvd_1d.CLK", site.pin "SLICE_X28Y95.CLK"
6.207ns - comp.pin "inst_mii_5/inst_encap/new_frame_flag_dly<15>.CLK", site.pin "SLICE_X28Y98.CLK"
6.034ns - comp.pin "inst_encap_fiber_port5/flag_recv_sfd.CLK", site.pin "SLICE_X28Y99.CLK"
6.149ns - comp.pin "inst_mii_5/inst_encap/new_frame_flag_dly<7>.CLK", site.pin "SLICE_X28Y100.CLK"
6.438ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/txcrc/Crc<31>.CLK", site.pin "SLICE_X28Y107.CLK"
6.670ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/txcrc/Crc<16>.CLK", site.pin "SLICE_X28Y108.CLK"
6.486ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/txcrc/Crc<21>.CLK", site.pin "SLICE_X28Y109.CLK"
5.753ns - comp.pin "inst_encap_fiber_port5/rx_int_pulse.CLK", site.pin "SLICE_X29Y95.CLK"
6.034ns - comp.pin "inst_mii_5/inst_encap/new_frame_flag_dly<3>.CLK", site.pin "SLICE_X29Y99.CLK"
5.965ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/rx_en_sync<1>.CLK", site.pin "SLICE_X29Y101.CLK"
6.438ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/txcrc/Crc<3>.CLK", site.pin "SLICE_X29Y107.CLK"
6.670ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/txcrc/Crc<10>.CLK", site.pin "SLICE_X29Y108.CLK"
6.486ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/txcrc/Crc<25>.CLK", site.pin "SLICE_X29Y109.CLK"
6.657ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/txcrc/Crc<23>.CLK", site.pin "SLICE_X29Y110.CLK"
6.422ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/rx_error.CLK", site.pin "SLICE_X30Y100.CLK"
6.539ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/vld_pkt_recvd.CLK", site.pin "SLICE_X30Y102.CLK"
6.892ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/rxd_r<3>.CLK", site.pin "SLICE_X30Y110.CLK"
6.684ns - comp.pin "pcs_pma_fiber_example_design_f12/core_wrapper/gig_eth_pcs_pma_core_0/BU2/N20.CLK", site.pin "SLICE_X31Y107.CLK"
6.850ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/txcrc/Crc<7>.CLK", site.pin "SLICE_X31Y108.CLK"
6.872ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/enable_crc.CLK", site.pin "SLICE_X33Y106.CLK"
6.473ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/rx_enable.CLK", site.pin "SLICE_X34Y98.CLK"
6.908ns - comp.pin "inst_mii_5/inst_encap/crc_ok.CLK", site.pin "SLICE_X36Y109.CLK"
8.013ns - comp.pin "inst_mii_5/inst_encap/drop_flag.CLK", site.pin "SLICE_X42Y104.CLK"
7.552ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/new_pkt_recvd.CLK", site.pin "SLICE_X42Y108.CLK"
7.368ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/status<2>.CLK", site.pin "SLICE_X42Y109.CLK"
7.896ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/giant_frame_flag.CLK", site.pin "SLICE_X43Y103.CLK"
8.013ns - comp.pin "inst_mii_5/inst_encap/err_code_int<2>.CLK", site.pin "SLICE_X43Y104.CLK"
8.119ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/dummy_frame_flag.CLK", site.pin "SLICE_X44Y103.CLK"
7.879ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/rec_nibble_cnten.CLK", site.pin "SLICE_X44Y104.CLK"
7.840ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/status_FSM_FFd3-In1.CLK", site.pin "SLICE_X44Y106.CLK"
7.648ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/status_FSM_FFd3.CLK", site.pin "SLICE_X44Y108.CLK"
8.100ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/runt_frame_flag.CLK", site.pin "SLICE_X45Y102.CLK"
8.119ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/N16.CLK", site.pin "SLICE_X45Y103.CLK"
7.648ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/crc_init_en.CLK", site.pin "SLICE_X45Y108.CLK"
7.617ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/preamble_cntr<3>.CLK", site.pin "SLICE_X48Y109.CLK"
7.574ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/addr_rec_pack_last<10>.CLK", site.pin "SLICE_X48Y110.CLK"
7.615ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/addr_rec_pack_last<6>.CLK", site.pin "SLICE_X49Y108.CLK"
7.394ns - comp.pin "inst_mii_5/inst_encap/addr_rec_pack<11>.CLK", site.pin "SLICE_X50Y101.CLK"
7.850ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/temp_addr_rec_pack<12>.CLK", site.pin "SLICE_X50Y110.CLK"
7.789ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/addr_rec_pack_last<12>.CLK", site.pin "SLICE_X51Y108.CLK"
7.605ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/addr_rec_pack_last<4>.CLK", site.pin "SLICE_X51Y109.CLK"
9.368ns - comp.pin "inst_mii_5/inst_encap/frame_info_in<3>.CLK", site.pin "SLICE_X52Y78.CLK"
9.185ns - comp.pin "inst_mii_5/inst_encap/frame_info_in<19>.CLK", site.pin "SLICE_X52Y79.CLK"
8.972ns - comp.pin "inst_mii_5/inst_encap/frame_info_in<11>.CLK", site.pin "SLICE_X52Y81.CLK"
9.103ns - comp.pin "inst_mii_5/inst_encap/frame_len_byte_nocrc<7>.CLK", site.pin "SLICE_X52Y82.CLK"
9.368ns - comp.pin "inst_mii_5/inst_encap/frame_info_in<7>.CLK", site.pin "SLICE_X53Y78.CLK"
9.185ns - comp.pin "inst_mii_5/inst_encap/frame_info_in<23>.CLK", site.pin "SLICE_X53Y79.CLK"
8.394ns - comp.pin "inst_mii_5/inst_encap/frame_info_in<15>.CLK", site.pin "SLICE_X53Y92.CLK"
7.737ns - comp.pin "inst_mii_5/inst_encap/data_rec_pack<3>.CLK", site.pin "SLICE_X53Y101.CLK"
7.921ns - comp.pin "inst_mii_5/inst_encap/addr_rec_pack<7>.CLK", site.pin "SLICE_X53Y102.CLK"
9.158ns - comp.pin "inst_mii_5/inst_encap/frame_len_byte_nocrc<9>.CLK", site.pin "SLICE_X54Y82.CLK"
9.194ns - comp.pin "inst_mii_5/inst_encap/frame_info_in<26>.CLK", site.pin "SLICE_X55Y80.CLK"
9.144ns - comp.pin "inst_mii_5/inst_encap/frame_len_byte<1>.CLK", site.pin "SLICE_X55Y83.CLK"

raojp · 发表于 2018-3-7 13:39:49

下面是未使用BUFG的MII clk的delay report。从中可以发现，clk到fifo_info_wen和fifo_info_in[26:0]的延时差值可达3.1ns，极有可能导致写入信息不对。
Net "mac5_rxc_IBUF":
9.406ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram.CLKAWRCLK", site.pin "RAMB8_X3Y39.CLKAWRCLK"
7.698ns - comp.pin "inst_mii_5/inst_encap/inst_frame_buf/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram.CLKA", site.pin "RAMB16_X3Y50.CLKA"
7.936ns - comp.pin "inst_mii_5/inst_encap/inst_frame_buf/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram.CLKA", site.pin "RAMB16_X3Y48.CLKA"
7.807ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/temp_addr_rec_pack<3>.CLK", site.pin "SLICE_X50Y107.CLK"
7.789ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/temp_addr_rec_pack<7>.CLK", site.pin "SLICE_X50Y108.CLK"
7.605ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/temp_addr_rec_pack<11>.CLK", site.pin "SLICE_X50Y109.CLK"
7.258ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/rec_count_nibble<3>.CLK", site.pin "SLICE_X46Y100.CLK"
7.074ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/rec_count_nibble<7>.CLK", site.pin "SLICE_X46Y101.CLK"
8.372ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/rec_count_nibble<11>.CLK", site.pin "SLICE_X46Y102.CLK"
8.919ns - comp.pin "inst_mii_5/inst_encap/frame_len_byte<3>.CLK", site.pin "SLICE_X52Y83.CLK"
8.904ns - comp.pin "inst_mii_5/inst_encap/frame_len_byte<7>.CLK", site.pin "SLICE_X52Y84.CLK"
8.708ns - comp.pin "inst_mii_5/inst_encap/frame_len_byte<10>.CLK", site.pin "SLICE_X52Y85.CLK"
driver - comp.pin "mac5_rxc.I", site.pin "F8.I"
2.963ns - comp.pin "inst_encap_fiber_port5/mac_rxdv_1d.CLK0", site.pin "ILOGIC_X3Y116.CLK0"
2.776ns - comp.pin "inst_encap_fiber_port5/mac_rxerr_1d.CLK0", site.pin "ILOGIC_X3Y118.CLK0"
3.413ns - comp.pin "inst_encap_fiber_port5/mac_rxd_1d<0>.CLK0", site.pin "ILOGIC_X2Y117.CLK0"
3.149ns - comp.pin "inst_encap_fiber_port5/mac_rxd_1d<1>.CLK0", site.pin "ILOGIC_X2Y118.CLK0"
3.149ns - comp.pin "inst_encap_fiber_port5/mac_rxd_1d<2>.CLK0", site.pin "ILOGIC_X2Y119.CLK0"
2.776ns - comp.pin "inst_encap_fiber_port5/mac_rxd_1d<3>.CLK0", site.pin "ILOGIC_X3Y119.CLK0"
4.174ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<0>.CLK", site.pin "SLICE_X0Y100.CLK"
3.983ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2.CLK", site.pin "SLICE_X0Y102.CLK"
4.146ns - comp.pin "inst_encap_fiber_port2/rec_mac_pack_z_inst/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/Mmux_comp1_GND_222_o_MUX_12_o13.CLK", site.pin "SLICE_X0Y103.CLK"
3.488ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>.CLK", site.pin "SLICE_X0Y110.CLK"
3.535ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i.CLK", site.pin "SLICE_X4Y110.CLK"
3.120ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<3>.CLK", site.pin "SLICE_X6Y110.CLK"
3.301ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<7>.CLK", site.pin "SLICE_X7Y108.CLK"
3.300ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<3>.CLK", site.pin "SLICE_X7Y109.CLK"
3.120ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<7>.CLK", site.pin "SLICE_X7Y110.CLK"
3.591ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>.CLK", site.pin "SLICE_X9Y107.CLK"
3.771ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<5>.CLK", site.pin "SLICE_X11Y110.CLK"
3.873ns - comp.pin "inst_encap_fiber_port5/mac_rxerr_2d.CLK", site.pin "SLICE_X12Y107.CLK"
3.695ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>.CLK", site.pin "SLICE_X12Y108.CLK"
4.133ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<5>.CLK", site.pin "SLICE_X13Y103.CLK"
3.695ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>.CLK", site.pin "SLICE_X13Y108.CLK"
6.224ns - comp.pin "inst_encap_fiber_port5/mac_rxd_2d<3>.CLK", site.pin "SLICE_X23Y107.CLK"
6.056ns - comp.pin "inst_mii_5/inst_encap/frame_info_wen.CLK", site.pin "SLICE_X27Y101.CLK"
5.753ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/vld_pkt_recvd_1d.CLK", site.pin "SLICE_X28Y95.CLK"
6.207ns - comp.pin "inst_mii_5/inst_encap/new_frame_flag_dly<15>.CLK", site.pin "SLICE_X28Y98.CLK"
6.034ns - comp.pin "inst_encap_fiber_port5/flag_recv_sfd.CLK", site.pin "SLICE_X28Y99.CLK"
6.149ns - comp.pin "inst_mii_5/inst_encap/new_frame_flag_dly<7>.CLK", site.pin "SLICE_X28Y100.CLK"
6.438ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/txcrc/Crc<31>.CLK", site.pin "SLICE_X28Y107.CLK"
6.670ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/txcrc/Crc<16>.CLK", site.pin "SLICE_X28Y108.CLK"
6.486ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/txcrc/Crc<21>.CLK", site.pin "SLICE_X28Y109.CLK"
5.753ns - comp.pin "inst_encap_fiber_port5/rx_int_pulse.CLK", site.pin "SLICE_X29Y95.CLK"
6.034ns - comp.pin "inst_mii_5/inst_encap/new_frame_flag_dly<3>.CLK", site.pin "SLICE_X29Y99.CLK"
5.965ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/rx_en_sync<1>.CLK", site.pin "SLICE_X29Y101.CLK"
6.438ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/txcrc/Crc<3>.CLK", site.pin "SLICE_X29Y107.CLK"
6.670ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/txcrc/Crc<10>.CLK", site.pin "SLICE_X29Y108.CLK"
6.486ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/txcrc/Crc<25>.CLK", site.pin "SLICE_X29Y109.CLK"
6.657ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/txcrc/Crc<23>.CLK", site.pin "SLICE_X29Y110.CLK"
6.422ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/rx_error.CLK", site.pin "SLICE_X30Y100.CLK"
6.539ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/vld_pkt_recvd.CLK", site.pin "SLICE_X30Y102.CLK"
6.892ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/rxd_r<3>.CLK", site.pin "SLICE_X30Y110.CLK"
6.684ns - comp.pin "pcs_pma_fiber_example_design_f12/core_wrapper/gig_eth_pcs_pma_core_0/BU2/N20.CLK", site.pin "SLICE_X31Y107.CLK"
6.850ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/txcrc/Crc<7>.CLK", site.pin "SLICE_X31Y108.CLK"
6.872ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/enable_crc.CLK", site.pin "SLICE_X33Y106.CLK"
6.473ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/rx_enable.CLK", site.pin "SLICE_X34Y98.CLK"
6.908ns - comp.pin "inst_mii_5/inst_encap/crc_ok.CLK", site.pin "SLICE_X36Y109.CLK"
8.013ns - comp.pin "inst_mii_5/inst_encap/drop_flag.CLK", site.pin "SLICE_X42Y104.CLK"
7.552ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/new_pkt_recvd.CLK", site.pin "SLICE_X42Y108.CLK"
7.368ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/status<2>.CLK", site.pin "SLICE_X42Y109.CLK"
7.896ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/giant_frame_flag.CLK", site.pin "SLICE_X43Y103.CLK"
8.013ns - comp.pin "inst_mii_5/inst_encap/err_code_int<2>.CLK", site.pin "SLICE_X43Y104.CLK"
8.119ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/dummy_frame_flag.CLK", site.pin "SLICE_X44Y103.CLK"
7.879ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/rec_nibble_cnten.CLK", site.pin "SLICE_X44Y104.CLK"
7.840ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/status_FSM_FFd3-In1.CLK", site.pin "SLICE_X44Y106.CLK"
7.648ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/status_FSM_FFd3.CLK", site.pin "SLICE_X44Y108.CLK"
8.100ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/runt_frame_flag.CLK", site.pin "SLICE_X45Y102.CLK"
8.119ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/N16.CLK", site.pin "SLICE_X45Y103.CLK"
7.648ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/crc_init_en.CLK", site.pin "SLICE_X45Y108.CLK"
7.617ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/preamble_cntr<3>.CLK", site.pin "SLICE_X48Y109.CLK"
7.574ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/addr_rec_pack_last<10>.CLK", site.pin "SLICE_X48Y110.CLK"
7.615ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/addr_rec_pack_last<6>.CLK", site.pin "SLICE_X49Y108.CLK"
7.394ns - comp.pin "inst_mii_5/inst_encap/addr_rec_pack<11>.CLK", site.pin "SLICE_X50Y101.CLK"
7.850ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/temp_addr_rec_pack<12>.CLK", site.pin "SLICE_X50Y110.CLK"
7.789ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/addr_rec_pack_last<12>.CLK", site.pin "SLICE_X51Y108.CLK"
7.605ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/addr_rec_pack_last<4>.CLK", site.pin "SLICE_X51Y109.CLK"
9.368ns - comp.pin "inst_mii_5/inst_encap/frame_info_in<3>.CLK", site.pin "SLICE_X52Y78.CLK"
9.185ns - comp.pin "inst_mii_5/inst_encap/frame_info_in<19>.CLK", site.pin "SLICE_X52Y79.CLK"
8.972ns - comp.pin "inst_mii_5/inst_encap/frame_info_in<11>.CLK", site.pin "SLICE_X52Y81.CLK"
9.103ns - comp.pin "inst_mii_5/inst_encap/frame_len_byte_nocrc<7>.CLK", site.pin "SLICE_X52Y82.CLK"
9.368ns - comp.pin "inst_mii_5/inst_encap/frame_info_in<7>.CLK", site.pin "SLICE_X53Y78.CLK"
9.185ns - comp.pin "inst_mii_5/inst_encap/frame_info_in<23>.CLK", site.pin "SLICE_X53Y79.CLK"
8.394ns - comp.pin "inst_mii_5/inst_encap/frame_info_in<15>.CLK", site.pin "SLICE_X53Y92.CLK"
7.737ns - comp.pin "inst_mii_5/inst_encap/data_rec_pack<3>.CLK", site.pin "SLICE_X53Y101.CLK"
7.921ns - comp.pin "inst_mii_5/inst_encap/addr_rec_pack<7>.CLK", site.pin "SLICE_X53Y102.CLK"
9.158ns - comp.pin "inst_mii_5/inst_encap/frame_len_byte_nocrc<9>.CLK", site.pin "SLICE_X54Y82.CLK"
9.194ns - comp.pin "inst_mii_5/inst_encap/frame_info_in<26>.CLK", site.pin "SLICE_X55Y80.CLK"
9.144ns - comp.pin "inst_mii_5/inst_encap/frame_len_byte<1>.CLK", site.pin "SLICE_X55Y83.CLK"

谁枫而飘 · 发表于 2018-3-7 14:27:23

如果时钟的负载少的话，可以不用接入GCLK

raojp · 发表于 2018-3-8 08:18:11

本帖最后由 raojp 于 2018-3-8 08:23 编辑

其实负载真心不多，fanout不超过100，但是曾经出过两个16-bit的地址计数器在同一时钟周期（状态机的某个状态下）关联变化，其中一个计数器就出现了因为高低位变化时间不一致导致的错误（如从16'bxxxx_xxxx_xxxx_0110变化到16'bxxxx_xxxx_xxxx_1000时，错误地变成16'bxxxx_xxxx_xxxx_1010），通过修改逻辑，避免了该问题，但看.par文件中的报告，还是有点心虚。
以下是Generating clock report中关于MII时钟的部分，可以看到分配到bufg上的时钟clock skew很小，在0.6ns量级，而非bufg时钟树上的时钟则skew高达7.2ns。
+---------------------+--------------+------+------+------------+-------------+
|       Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|    mac7_rxc_IBUF |       Local|    | 93 |  7.219    |  9.894    |
+---------------------+--------------+------+------+------------+-------------+
|    mac6_rxc_IBUF |       Local|    | 91 |  2.317    |  5.092    |
+---------------------+--------------+------+------+------------+-------------+
|    mac5_rxc_IBUF |       Local|    | 89 |  5.447    |  8.213    |
+---------------------+--------------+------+------+------------+-------------+
|    mac4_rxc_bufg | BUFGMUX_X3Y13|Yes | 90 |  0.605    |  2.314    |
+---------------------+--------------+------+------+------------+-------------+
|    mac3_rxc_bufg |  BUFGMUX_X3Y6|Yes | 92 |  0.673    |  2.386    |
+---------------------+--------------+------+------+------------+-------------+
|    mac2_rxc_bufg |  BUFGMUX_X3Y5|Yes | 90 |  0.671    |  2.386    |
+---------------------+--------------+------+------+------------+-------------+
|    mac1_rxc_bufg |  BUFGMUX_X2Y1|Yes | 88 |  0.676    |  2.386    |
+---------------------+--------------+------+------+------------+-------------+
|    mac0_rxc_bufg | BUFGMUX_X3Y14|Yes | 93 |  0.617    |  2.329    |
+---------------------+--------------+------+------+------------+-------------+

raojp · 发表于 2018-3-9 09:24:34

对无法使用BUFG的时钟施加约束：NET "mac5_rxc" MAXSKEW = 0.25 ns;
效果挺好的，可以看到时钟到temp_addr_rec_pack, addr_rec_pack_last等相关逻辑的delay从2.815ns~3.303ns, skew为0.488ns，改善很多。不过还是有些担心，在高低温下时序时序是否会出问题，毕竟0.488ns的歪斜已经和setup time相当了，与此对应，使用bufg的时钟skew才0.040ns。

Net "mac5_rxc_IBUF":
3.331ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram.CLKAWRCLK", site.pin "RAMB8_X0Y56.CLKAWRCLK"
4.016ns - comp.pin "inst_mii_5/inst_encap/inst_frame_buf/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram.CLKA", site.pin "RAMB16_X0Y50.CLKA"
4.253ns - comp.pin "inst_mii_5/inst_encap/inst_frame_buf/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram.CLKA", site.pin "RAMB16_X0Y48.CLKA"
2.851ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/temp_addr_rec_pack<3>.CLK", site.pin "SLICE_X0Y122.CLK"
2.847ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/temp_addr_rec_pack<7>.CLK", site.pin "SLICE_X0Y123.CLK"
2.815ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/temp_addr_rec_pack<11>.CLK", site.pin "SLICE_X0Y124.CLK"
2.857ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/temp_addr_rec_pack<12>.CLK", site.pin "SLICE_X0Y125.CLK"
3.088ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/rec_count_nibble<3>.CLK", site.pin "SLICE_X0Y118.CLK"
3.114ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/rec_count_nibble<7>.CLK", site.pin "SLICE_X0Y119.CLK"
3.043ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/rec_count_nibble<11>.CLK", site.pin "SLICE_X0Y120.CLK"
3.631ns - comp.pin "inst_mii_5/inst_encap/frame_len_byte<3>.CLK", site.pin "SLICE_X2Y110.CLK"
3.547ns - comp.pin "inst_mii_5/inst_encap/frame_len_byte<7>.CLK", site.pin "SLICE_X2Y111.CLK"
3.586ns - comp.pin "inst_mii_5/inst_encap/frame_len_byte<10>.CLK", site.pin "SLICE_X2Y112.CLK"
driver - comp.pin "mac5_rxc.I", site.pin "F8.I"
2.988ns - comp.pin "inst_mii_5/mac_rxdv_1d.CLK0", site.pin "ILOGIC_X3Y116.CLK0"
2.862ns - comp.pin "inst_mii_5/mac_rxerr_1d.CLK0", site.pin "ILOGIC_X3Y118.CLK0"
3.400ns - comp.pin "inst_mii_5/mac_rxd_1d<0>.CLK0", site.pin "ILOGIC_X2Y117.CLK0"
3.240ns - comp.pin "inst_mii_5/mac_rxd_1d<1>.CLK0", site.pin "ILOGIC_X2Y118.CLK0"
3.240ns - comp.pin "inst_mii_5/mac_rxd_1d<2>.CLK0", site.pin "ILOGIC_X2Y119.CLK0"
2.862ns - comp.pin "inst_mii_5/mac_rxd_1d<3>.CLK0", site.pin "ILOGIC_X3Y119.CLK0"
3.587ns - comp.pin "inst_mii_5/inst_encap/frame_len_byte_nocrc<9>.CLK", site.pin "SLICE_X0Y110.CLK"
3.505ns - comp.pin "inst_mii_5/inst_encap/crc_ok.CLK", site.pin "SLICE_X0Y113.CLK"
3.319ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/txcrc/Crc<31>.CLK", site.pin "SLICE_X0Y114.CLK"
3.324ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/rx_en_sync<1>.CLK", site.pin "SLICE_X0Y115.CLK"
3.272ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2.CLK", site.pin "SLICE_X0Y117.CLK"
3.037ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<5>.CLK", site.pin "SLICE_X0Y121.CLK"
3.505ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/txcrc/Crc<25>.CLK", site.pin "SLICE_X1Y113.CLK"
3.324ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/N8.CLK", site.pin "SLICE_X1Y115.CLK"
3.270ns - comp.pin "inst_mii_5/inst_encap/addr_rec_pack<7>.CLK", site.pin "SLICE_X1Y116.CLK"
3.272ns - comp.pin "inst_mii_5/inst_encap/err_code_int<2>.CLK", site.pin "SLICE_X1Y117.CLK"
3.088ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<3>.CLK", site.pin "SLICE_X1Y118.CLK"
3.114ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>.CLK", site.pin "SLICE_X1Y119.CLK"
3.043ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>.CLK", site.pin "SLICE_X1Y120.CLK"
3.028ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/status<2>_inv.CLK", site.pin "SLICE_X1Y121.CLK"
2.851ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/giant_frame_flag.CLK", site.pin "SLICE_X1Y122.CLK"
2.847ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/new_pkt_recvd.CLK", site.pin "SLICE_X1Y123.CLK"
2.815ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/addr_rec_pack_last<10>.CLK", site.pin "SLICE_X1Y124.CLK"
2.865ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/addr_rec_pack_last<4>.CLK", site.pin "SLICE_X1Y125.CLK"
3.482ns - comp.pin "inst_mii_5/inst_encap/frame_info_in<11>.CLK", site.pin "SLICE_X2Y113.CLK"
3.394ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/txcrc/Crc<16>.CLK", site.pin "SLICE_X2Y114.CLK"
3.279ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/_n0393.CLK", site.pin "SLICE_X2Y115.CLK"
3.289ns - comp.pin "inst_mii_5/inst_encap/new_frame_flag_dly<11>.CLK", site.pin "SLICE_X2Y116.CLK"
3.236ns - comp.pin "inst_mii_5/inst_encap/new_frame_flag_dly<15>.CLK", site.pin "SLICE_X2Y117.CLK"
3.147ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/crc_init_en.CLK", site.pin "SLICE_X2Y118.CLK"
3.074ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>.CLK", site.pin "SLICE_X2Y119.CLK"
3.040ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/N8.CLK", site.pin "SLICE_X2Y120.CLK"
3.007ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<7>.CLK", site.pin "SLICE_X2Y121.CLK"
2.898ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<5>.CLK", site.pin "SLICE_X2Y122.CLK"
2.867ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<3>.CLK", site.pin "SLICE_X2Y123.CLK"
2.852ns - comp.pin "inst_mii_5/inst_encap/drop_flag.CLK", site.pin "SLICE_X2Y124.CLK"
2.887ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>.CLK", site.pin "SLICE_X2Y125.CLK"
3.726ns - comp.pin "inst_mii_5/inst_encap/data_rec_pack<3>.CLK", site.pin "SLICE_X3Y109.CLK"
3.631ns - comp.pin "inst_mii_5/inst_encap/frame_info_in<15>.CLK", site.pin "SLICE_X3Y110.CLK"
3.547ns - comp.pin "inst_mii_5/inst_encap/frame_info_in<6>.CLK", site.pin "SLICE_X3Y111.CLK"
3.482ns - comp.pin "inst_mii_5/inst_encap/frame_info_in<7>.CLK", site.pin "SLICE_X3Y113.CLK"
3.394ns - comp.pin "inst_mii_5/inst_encap/frame_len_byte<1>.CLK", site.pin "SLICE_X3Y114.CLK"
3.289ns - comp.pin "inst_mii_5/inst_encap/addr_rec_pack<3>.CLK", site.pin "SLICE_X3Y116.CLK"
3.236ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/txcrc/Crc<21>.CLK", site.pin "SLICE_X3Y117.CLK"
3.147ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/preamble_cntr<3>.CLK", site.pin "SLICE_X3Y118.CLK"
3.074ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/dummy_frame_flag.CLK", site.pin "SLICE_X3Y119.CLK"
3.040ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/vld_pkt_recvd.CLK", site.pin "SLICE_X3Y120.CLK"
3.007ns - comp.pin "inst_mii_5/mac_rxd_2d<3>.CLK", site.pin "SLICE_X3Y121.CLK"
2.898ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/addr_rec_pack_last<6>.CLK", site.pin "SLICE_X3Y122.CLK"
2.867ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i.CLK", site.pin "SLICE_X3Y123.CLK"
2.854ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/runt_frame_flag.CLK", site.pin "SLICE_X3Y124.CLK"
3.541ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/rxd_r<3>.CLK", site.pin "SLICE_X4Y108.CLK"
3.398ns - comp.pin "inst_mii_5/inst_encap/frame_len_byte_nocrc<7>.CLK", site.pin "SLICE_X4Y111.CLK"
3.303ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/addr_rec_pack_last<12>.CLK", site.pin "SLICE_X4Y112.CLK"
3.197ns - comp.pin "inst_mii_5/inst_encap/addr_rec_pack<11>.CLK", site.pin "SLICE_X4Y114.CLK"
3.157ns - comp.pin "inst_mii_5/inst_encap/new_frame_flag_dly<3>.CLK", site.pin "SLICE_X4Y115.CLK"
2.956ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<7>.CLK", site.pin "SLICE_X4Y118.CLK"
3.626ns - comp.pin "inst_mii_5/inst_encap/frame_info_in<22>.CLK", site.pin "SLICE_X5Y107.CLK"
3.541ns - comp.pin "inst_mii_5/inst_encap/frame_info_in<23>.CLK", site.pin "SLICE_X5Y108.CLK"
3.433ns - comp.pin "inst_mii_5/inst_encap/frame_info_in<19>.CLK", site.pin "SLICE_X5Y109.CLK"
3.443ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<7>.CLK", site.pin "SLICE_X5Y110.CLK"
3.398ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/txcrc/Crc<3>.CLK", site.pin "SLICE_X5Y111.CLK"
3.303ns - comp.pin "inst_mii_5/inst_encap/new_frame_flag_dly<7>.CLK", site.pin "SLICE_X5Y112.CLK"
3.196ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<7>.CLK", site.pin "SLICE_X5Y113.CLK"
3.157ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/rx_enable.CLK", site.pin "SLICE_X5Y115.CLK"
2.926ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/status_FSM_FFd3.CLK", site.pin "SLICE_X5Y119.CLK"
2.797ns - comp.pin "inst_mii_5/inst_encap/inst_info_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>.CLK", site.pin "SLICE_X5Y120.CLK"
3.241ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/txcrc/Crc<7>.CLK", site.pin "SLICE_X6Y111.CLK"
3.241ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/txcrc/Crc<10>.CLK", site.pin "SLICE_X7Y111.CLK"
3.168ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/enable_crc.CLK", site.pin "SLICE_X7Y112.CLK"
3.460ns - comp.pin "inst_mii_5/inst_encap/rec_mac_pack_inst0/rx_error.CLK", site.pin "SLICE_X8Y110.CLK"
3.468ns - comp.pin "inst_mii_5/flag_recv_sfd.CLK", site.pin "SLICE_X8Y111.CLK"

cattutu · 发表于 2018-3-10 13:24:09

sparten不清楚了但是你为什么要这么多gclk？改成区域declk嘛

谁枫而飘 · 发表于 2018-3-14 13:53:57

回复 8# cattutu

对头，xilinx的可以这样用，用区域时钟，altera的怎么办呢？没有看见什么区域时钟

guyefeng123321 · 发表于 2018-3-15 16:00:29

修改 GTX CLK 的.v文件，使用已经经过bufg的clk

[求助] GCLK不够用怎么办

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