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[资料] Design of High-Performance CMOS Voltage-Controlled Oscillators

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发表于 2017-2-18 11:23:34 | 显示全部楼层 |阅读模式

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This book is organized as follows. In Chapter 2 we first introduce somebasic knowledge about PLLs. We briefly discuss each of the building blocks ina PLL and apply linear analysis for phase-locked state. Based on linear analysiswe try to understand how each building block contributes phase noise to thePLL. We will also discuss the relationship between phase noise and timingjitter. In Chapter 3, we introduce definitions for single-sideband (SSB) phasenoise and timing jitter, and discuss their relationship. Then, in Chapter 4, wereview some of the existing phase noise models for oscillators. By discussingthe advantages and disadvantages ofthese models we introduce our motivationfor this work. In Chapter 5 we develop a theoretical frame work for CMOS ringoscillator phase noise analysis. Our VCO phase noise analysis method serves asa good compromise between accuracy and computation complexity. Later we apply our theoretical analysis and present a new CMOS ring oscillator designin Chapter 6. Additionally we develop jitter analysis to include ring oscillatorswith memory delay cells. Two PLL designs are presented in Chapter 7 withmeasurement results. Finally we provide some conclusions in Chapter 8.

Design of High-Performance CMOS Voltage-Controlled Oscillators.pdf

13.75 MB, 下载次数: 1018 , 下载积分: 资产 -5 信元, 下载支出 5 信元

VCO

发表于 2017-2-18 15:34:06 | 显示全部楼层
by Liang Dai and Ramesh Harjani
2003
发表于 2017-2-18 18:05:01 | 显示全部楼层
kankan
发表于 2017-2-18 23:19:08 | 显示全部楼层
looks ok.
发表于 2017-2-19 16:24:45 | 显示全部楼层
thanks for sharing
发表于 2017-2-19 18:04:47 | 显示全部楼层
thanks.good
发表于 2017-2-19 21:13:48 | 显示全部楼层
好的资料,谢谢分享!
发表于 2017-2-19 23:10:29 | 显示全部楼层
Thanks for your sharing
发表于 2017-2-19 23:18:47 | 显示全部楼层
THX for sharing
发表于 2017-2-22 13:19:26 | 显示全部楼层
回复 4# pangguai

谢谢分享
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