Design of High-Performance CMOS Voltage-Controlled Oscillators

leiya21

This book is organized as follows. In Chapter 2 we first introduce somebasic knowledge about PLLs. We briefly discuss each of the building blocks ina PLL and apply linear analysis for phase-locked state. Based on linear analysiswe try to understand how each building block contributes phase noise to thePLL. We will also discuss the relationship between phase noise and timingjitter. In Chapter 3, we introduce definitions for single-sideband (SSB) phasenoise and timing jitter, and discuss their relationship. Then, in Chapter 4, wereview some of the existing phase noise models for oscillators. By discussingthe advantages and disadvantages ofthese models we introduce our motivationfor this work. In Chapter 5 we develop a theoretical frame work for CMOS ringoscillator phase noise analysis. Our VCO phase noise analysis method serves asa good compromise between accuracy and computation complexity. Later we apply our theoretical analysis and present a new CMOS ring oscillator designin Chapter 6. Additionally we develop jitter analysis to include ring oscillatorswith memory delay cells. Two PLL designs are presented in Chapter 7 withmeasurement results. Finally we provide some conclusions in Chapter 8.

lhyi

by Liang Dai and Ramesh Harjani
2003

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pangguai

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p20578

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jyhking

回复 4# pangguai

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