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发表于 2016-9-22 17:54:00
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SystemVerilog 上的解释:
The immediate assume statement specifies that its expression is assumed to hold. For example, immediate
assume statements can be used with formal verification tools to specify assumptions on design inputs that
constrain the verification computation. When used in this way, they specify the expected behavior of the
environment of the design as opposed to that of the design itself. In simulation, an immediate assume may
behave as an immediate assert to verify that the environment behaves as assumed. A simulation tool shall
provide the capability to check the immediate assume statement in this way.
仿真时,assert与assume用途一样
形式验证时,assume可用于约束DUT的输入,用于过滤不需要的时序组合 |
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