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最近run LVS, 发现了一个比较奇特的问题,请大神帮忙看一下,多谢!
如下面报告所述,L与S对不上,通过具体对比,我发现,L与S对比的cell就不是相同的cell,S是Xu_dphy_sync/Xtxdata_out_ana_1_sync2_reg_6_,而根据L中的坐标的来的cell却是Xu_dphy_sync/Xtxdata_out_ana_1_sync2_reg_5_,不知道calibre为什么会比错对象。
************************************************************************************************************** INCORRECT OBJECTS **************************************************************************************************************
LEGEND: -------
ne = Naming Error (same layoutname found in source circuit, but object was matched otherwise).
************************************************************************************************************** INSTANCES OF CELLS WITH NON-FLOATING EXTRA PINS
DISC# LAYOUTNAME SOURCE NAME **************************************************************************************************************
1 X13/X712(212.155,4.520) DRNQV0_9TR35 Xu_dphy_sync/Xtxdata_out_ana_1_sync2_reg_6_ DRNQV0_9TR35 X13/X712/3:930 ** missing pin ** Xu_dphy_sync/Xtxdata_out_ana_1_sync2_reg_6_/cn ?Xu_dphy_sync/txdata_out_ana_1_sync[6]
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2 X12/X1248(63.115,6.320) DRNQV0_9TR35 Xu_dphy_sync/Xtxdata_out_ana_0_sync2_reg_7_ DRNQV0_9TR35 X12/X1248/5:X12/32730 **missing pin ** Xu_dphy_sync/Xtxdata_out_ana_0_sync2_reg_7_/c ? Xu_dphy_sync/n19
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3 X11/X1522(159.910,17.980) DRNQV0_9TR35 Xu_dphy_sync/Xclk_lptx_ck_sync2_reg_1_ DRNQV0_9TR35 X11/X1522/5:X11/35802 ** missing pin ** Xu_dphy_sync/Xclk_lptx_ck_sync2_reg_1_/c ? Xu_dphy_sync/n37
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4 X11/X1515(132.640,15.320) DRNQV0_9TR35 Xu_dphy_sync/Xtxclklane_hsdata_sync2_reg_3_ DRNQV0_9TR35 X11/X1515/3:X11/10379 **missing pin ** Xu_dphy_sync/Xtxclklane_hsdata_sync2_reg_3_/cn ?Xu_dphy_sync/txclklane_hsdata_sync[3]
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5 X11/X1514(132.235,14.380) DRNQV0_9TR35 Xu_poweron/Xmaster_sel_sync2_reg DRNQV0_9TR35 X11/X1514/5:X11/35021 ** missing pin ** Xu_poweron/Xmaster_sel_sync2_reg/c ? Xu_poweron/n40
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6 X11/X1513(132.235,13.520) DRNQV0_9TR35 Xu_dphy_sync/Xtxclklane_hsdata_sync2_reg_4_ DRNQV0_9TR35 X11/X1513/3:X11/10389 ** missing pin ** Xu_dphy_sync/Xtxclklane_hsdata_sync2_reg_4_/cn ?Xu_dphy_sync/txclklane_hsdata_sync[4]
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7 X10/X1452(128.455,26.980) DRNQV0_9TR35 Xu_datalane1_ctrl/Xu_txdata_ctrl/Xtxrequesths_sync2_reg DRNQV0_9TR35 X10/X1452/3:X10/29125 ** missing pin ** Xu_datalane1_ctrl/Xu_txdata_ctrl/Xtxrequesths_sync2_reg/cn ?Xu_datalane1_ctrl/Xu_txdata_ctrl/n214
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8 X10/X1450(126.025,24.320) DRNQV0_9TR35 Xu_poweron/Xulps_enter_0_sync2_reg DRNQV0_9TR35 X10/X1450/5:X10/29015 ** missing pin ** Xu_poweron/Xulps_enter_0_sync2_reg/c ? Xu_poweron/n52
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9 X10/X621(270.340,23.380) SDRNQV0_9TR35 Xu_datalane0_ctrl/Xu_data_turn_rx/Xjump_to_ta_get_narrow_reg SDRNQV0_9TR35 X10/X621/6:2218 ** missing pin **Xu_datalane0_ctrl/Xu_data_turn_rx/Xjump_to_ta_get_narrow_reg/R ? n374
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10 X9/X1481(211.480,31.520) DRNQV0_9TR35 Xu_clklane_ctrl/Xu_txclk_hs/Xtclk_prepostsync2_reg_3_ DRNQV0_9TR35 X9/X1481/5:X9/25586 ** missing pin ** Xu_clklane_ctrl/Xu_txclk_hs/Xtclk_prepostsync2_reg_3_/c ?Xu_clklane_ctrl/Xu_txclk_hs/n48
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11 X9/X1462(51.640,29.720) DRNQV0_9TR35 Xu_datalane0_ctrl/Xu_txdata_hswr/Xen_txdata_hsync2_reg DRNQV0_9TR35 X9/X1462/5:X9/29170 ** missing pin ** Xu_datalane0_ctrl/Xu_txdata_hswr/Xen_txdata_hsync2_reg/c ?Xu_datalane0_ctrl/Xu_txdata_hswr/n54
--------------------------------------------------------------------------------------------------------------
12 X9/X595(206.350,30.580) SDRNQV0_9TR35 Xu_clklane_ctrl/Xu_txclk_hs/Xtclk_prepostsync_reg_1_ SDRNQV0_9TR35 X9/X595/5:2134 ** missing pin ** Xu_clklane_ctrl/Xu_txclk_hs/Xtclk_prepostsync_reg_1_/cn ?n365
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13 X8/X1556(259.135,37.780) DRNQV0_9TR35 Xu_datalane0_ctrl/Xu_data_turn_rx/Xenable_sync2_reg DRNQV0_9TR35 X8/X1556/5:X8/38012 ** missing pin ** Xu_datalane0_ctrl/Xu_data_turn_rx/Xenable_sync2_reg/c ?Xu_datalane0_ctrl/Xu_data_turn_rx/n231
--------------------------------------------------------------------------------------------------------------
14 X8/X1553(205.810,39.580) DRNQV0_9TR35 Xu_clklane_ctrl/Xu_filter_ck/Xreg1_reg_1_ DRNQV0_9TR35 X8/X1553/5:X8/36682 **missing pin ** Xu_clklane_ctrl/Xu_filter_ck/Xreg1_reg_1_/c ?Xu_clklane_ctrl/Xu_filter_ck/n1
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15 X8/X1552(205.000,41.380) DRNQV0_9TR35 Xu_clklane_ctrl/Xu_filter_ck/Xreg0_reg_1_ DRNQV0_9TR35 X8/X1552/3:4806 ** missing pin ** Xu_clklane_ctrl/Xu_filter_ck/Xreg0_reg_1_/cn ?Xu_clklane_ctrl/Xu_filter_ck/n2
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16 X8/X1550(198.925,39.580) DRNQV0_9TR35 Xu_clklane_ctrl/Xu_txclk_hs/Xenableclksync2_reg DRNQV0_9TR35 X8/X1550/5:X8/36465 ** missing pin ** Xu_clklane_ctrl/Xu_txclk_hs/Xenableclksync2_reg/c ?Xu_clklane_ctrl/Xu_txclk_hs/n50
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17 X8/X1546(194.470,35.980) DRNQV0_9TR35 Xu_clklane_ctrl/Xu_txclk_ctrl/Xclkready_hsync2_reg DRNQV0_9TR35 X8/X1546/5:X8/36295 ** missing pin ** Xu_clklane_ctrl/Xu_txclk_ctrl/Xclkready_hsync2_reg/c ?Xu_clklane_ctrl/Xu_txclk_ctrl/n255
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18 X8/X1536(47.455,38.720) DRNQV0_9TR35 Xu_datalane0_ctrl/Xu_txdata_hswr/Xdirection_sync2_reg DRNQV0_9TR35 X8/X1536/5:X8/32783 ** missing pin ** Xu_datalane0_ctrl/Xu_txdata_hswr/Xdirection_sync2_reg/c ?Xu_datalane0_ctrl/Xu_txdata_hswr/n58
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19 X8/X1534(40.165,39.580) DRNQV0_9TR35 Xu_datalane0_ctrl/Xu_txdata_hswr/Xtdata_trailsync2_reg_3_ DRNQV0_9TR35 X8/X1534/5:X8/32618 ** missing pin ** Xu_datalane0_ctrl/Xu_txdata_hswr/Xtdata_trailsync2_reg_3_/c ?Xu_datalane0_ctrl/Xu_txdata_hswr/n50
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20 X8/X682(258.190,38.720) SDRNQV0_9TR35 Xu_datalane0_ctrl/Xu_data_turn_rx/Xenable_sync1_reg SDRNQV0_9TR35 X8/X682/5:X8/30451 ** missing pin ** Xu_datalane0_ctrl/Xu_data_turn_rx/Xenable_sync1_reg/cn ?Xu_datalane0_ctrl/Xu_rxdata_hs_ctrl/n403
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21 X8/X639(186.910,42.320) SDRNQV0_9TR35 Xu_clklane_ctrl/Xu_txclk_ctrl/Xlp_tx_reg_0_ SDRNQV0_9TR35 X8/X639/5:4787 ** missing pin ** Xu_clklane_ctrl/Xu_txclk_ctrl/Xlp_tx_reg_0_/cn ?Xu_datalane1_ctrl/Xu_txdata_esc/timeenter_sync[0]
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22 X7/X1502(202.435,49.520) DRNQV0_9TR35 Xu_clklane_ctrl/Xu_txclk_esc/Xtimeenter_sync2_reg_0_ DRNQV0_9TR35 X7/X1502/3:4482 ** missing pin ** Xu_clklane_ctrl/Xu_txclk_esc/Xtimeenter_sync2_reg_0_/cn ?Xu_clklane_ctrl/Xu_txclk_esc/n51
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23 X7/X1499(187.585,45.920) DRNQV0_9TR35 Xu_clklane_ctrl/Xu_txclk_ctrl/Xmaster_sel_sync2_reg DRNQV0_9TR35 X7/X1499/3:X7/37052 ** missing pin ** Xu_clklane_ctrl/Xu_txclk_ctrl/Xmaster_sel_sync2_reg/cn ?Xu_clklane_ctrl/Xu_txclk_ctrl/n253
--------------------------------------------------------------------------------------------------------------
24 X7/X1498(185.830,43.180) DRNQV0_9TR35 Xu_clklane_ctrl/Xu_txclk_ctrl/Xtxrequesths_sync2_reg DRNQV0_9TR35 X7/X1498/5:X7/37053 ** missing pin ** Xu_clklane_ctrl/Xu_txclk_ctrl/Xtxrequesths_sync2_reg/c ?Xu_clklane_ctrl/Xu_txclk_ctrl/n250
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25 X7/X1491(117.790,46.780) DRNQV0_9TR35 Xu_datalane0_ctrl/Xu_mipi_fifo_0/Xu_sync_r2w/Xwq2_rptr_reg_1_ DRNQV0_9TR35 X7/X1491/5:X7/35792 ** missing pin **Xu_datalane0_ctrl/Xu_mipi_fifo_0/Xu_sync_r2w/Xwq2_rptr_reg_1_/c ?Xu_datalane0_ctrl/Xu_mipi_fifo_0/Xu_sync_r2w/n2
--------------------------------------------------------------------------------------------------------------
26 X7/X1486(89.980,44.980) DRNQV0_9TR35 Xu_datalane1_ctrl/Xu_rxdata_escp/Xsample3_reg DRNQV0_9TR35 X7/X1486/5:X7/35089 ** missing pin ** Xu_datalane1_ctrl/Xu_rxdata_escp/Xsample3_reg/c ?Xu_datalane1_ctrl/Xu_rxdata_escp/n173
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27 X7/X1485(62.305,46.780) DRNQV0_9TR35 Xu_datalane0_ctrl/Xu_txdata_esc/Xtimeenter_sync2_reg_1_ DRNQV0_9TR35 X7/X1485/5:X7/34502 ** missing pin ** Xu_datalane0_ctrl/Xu_txdata_esc/Xtimeenter_sync2_reg_1_/c ?Xu_datalane0_ctrl/Xu_txdata_esc/n124
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28 X7/X1484(61.765,47.720) DRNQV0_9TR35 Xu_datalane0_ctrl/Xu_txdata_esc/Xtimeenter_sync2_reg_0_ DRNQV0_9TR35 X7/X1484/3:X7/34503 ** missing pin ** Xu_datalane0_ctrl/Xu_txdata_esc/Xtimeenter_sync2_reg_0_/cn ?Xu_datalane0_ctrl/Xu_txdata_esc/n123
--------------------------------------------------------------------------------------------------------------
29 X7/X1483(61.765,45.920) DRNQV0_9TR35 Xu_datalane0_ctrl/Xu_txdata_esc/Xtimeenter_sync2_reg_2_ DRNQV0_9TR35 X7/X1483/5:X7/34501 ** missing pin ** Xu_datalane0_ctrl/Xu_txdata_esc/Xtimeenter_sync2_reg_2_/c ?Xu_datalane0_ctrl/Xu_txdata_esc/n141
--------------------------------------------------------------------------------------------------------------
30 X6/X925(205.945,50.380) DRNQV0_9TR35 Xu_clklane_ctrl/Xu_rxclk_ctrl/Xctrl_clk_miss_sync3_reg DRNQV0_9TR35 X6/X925/5:X6/16119 ** missing pin ** Xu_clklane_ctrl/Xu_rxclk_ctrl/Xctrl_clk_miss_sync3_reg/c ?Xu_clklane_ctrl/Xu_rxclk_ctrl/n190
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31 X6/X924(202.840,50.380) DRNQV0_9TR35 Xu_clklane_ctrl/Xu_txclk_esc/Xtimeenter_sync2_reg_2_ DRNQV0_9TR35 X6/X924/5:X6/16090 **missing pin ** Xu_clklane_ctrl/Xu_txclk_esc/Xtimeenter_sync2_reg_2_/c ?Xu_clklane_ctrl/Xu_txclk_esc/n54
--------------------------------------------------------------------------------------------------------------
32 X6/X921(186.100,52.180) DRNQV0_9TR35 Xu_datalane1_ctrl/Xu_txdata_esc/Xtimeexit_sync2_reg_2_ DRNQV0_9TR35 X6/X921/5:X6/15969 ** missing pin ** Xu_datalane1_ctrl/Xu_txdata_esc/Xtimeexit_sync2_reg_2_/c ?Xu_datalane1_ctrl/Xu_txdata_esc/n183
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33 X6/X916(56.365,53.120) DRNQV0_9TR35 Xu_datalane1_ctrl/Xu_txdata_hswr/Xen_datalane_sync2_reg DRNQV0_9TR35 X6/X916/3:X6/14801 ** missing pin ** Xu_datalane1_ctrl/Xu_txdata_hswr/Xen_datalane_sync2_reg/cn ?Xu_datalane1_ctrl/Xu_txdata_hswr/n63
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34 X6/X912(43.540,51.320) DRNQV0_9TR35 Xu_datalane1_ctrl/Xu_txdata_hswr/Xtdata_trailsync2_reg_0_ DRNQV0_9TR35 X6/X912/5:X6/14589 **missing pin ** Xu_datalane1_ctrl/Xu_txdata_hswr/Xtdata_trailsync2_reg_0_/c ?Xu_datalane1_ctrl/Xu_txdata_hswr/n46
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35 X6/X911(40.435,51.320) DRNQV0_9TR35 Xu_datalane1_ctrl/Xu_txdata_hswr/Xtdata_trailsync2_reg_1_ DRNQV0_9TR35 X6/X911/3:X6/14546 ** missing pin ** Xu_datalane1_ctrl/Xu_txdata_hswr/Xtdata_trailsync2_reg_1_/cn? Xu_datalane1_ctrl/Xu_txdata_hswr/n48
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36 X6/X909(12.355,51.320) DRNQV0_9TR35 Xu_datalane1_ctrl/Xu_mipi_fifo_1/Xu_sync_w2r/Xrq2_wptr_reg_0_ DRNQV0_9TR35 X6/X909/3:X6/14177 ** missing pin **Xu_datalane1_ctrl/Xu_mipi_fifo_1/Xu_sync_w2r/Xrq2_wptr_reg_0_/cn ?Xu_datalane1_ctrl/Xu_mipi_fifo_1/Xu_sync_w2r/n1
--------------------------------------------------------------------------------------------------------------
37 X6/X908(12.355,50.380) DRNQV0_9TR35 Xu_datalane1_ctrl/Xu_mipi_fifo_1/Xu_sync_w2r/Xrq2_wptr_reg_3_ DRNQV0_9TR35 X6/X908/5:X6/14176 ** missing pin ** Xu_datalane1_ctrl/Xu_mipi_fifo_1/Xu_sync_w2r/Xrq2_wptr_reg_3_/c? Xu_datalane1_ctrl/Xu_mipi_fifo_1/Xu_sync_w2r/n4
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38 X5/X929(116.980,53.980) DRNQV0_9TR35 Xu_datalane0_ctrl/Xu_mipi_fifo_0/Xu_sync_r2w/Xwq2_rptr_reg_3_ DRNQV0_9TR35 X5/X929/5:X5/19090 ** missing pin **Xu_datalane0_ctrl/Xu_mipi_fifo_0/Xu_sync_r2w/Xwq2_rptr_reg_3_/c ?Xu_datalane0_ctrl/Xu_mipi_fifo_0/Xu_sync_r2w/n4
--------------------------------------------------------------------------------------------------------------
39 X5/X928(116.575,54.920) DRNQV0_9TR35 Xu_datalane0_ctrl/Xu_mipi_fifo_0/Xu_sync_r2w/Xwq2_rptr_reg_4_ DRNQV0_9TR35 X5/X928/3:X5/19086 ** missing pin **Xu_datalane0_ctrl/Xu_mipi_fifo_0/Xu_sync_r2w/Xwq2_rptr_reg_4_/cn ?Xu_datalane0_ctrl/Xu_mipi_fifo_0/Xu_sync_r2w/n5
--------------------------------------------------------------------------------------------------------------
40 X5/X340(15.460,54.920) SDRNQV0_9TR35 Xu_datalane1_ctrl/Xu_mipi_fifo_1/Xu_sync_r2w/Xwq1_rptr_reg_2_ SDRNQV0_9TR35 X5/X340/5:X5/17571 ** missing pin **Xu_datalane1_ctrl/Xu_mipi_fifo_1/Xu_sync_r2w/Xwq1_rptr_reg_2_/cn ?Xu_datalane1_ctrl/Xu_mipi_fifo_1/Xu_sync_r2w/n1 |