Logic Circuit Design -- Selected Methods

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Shimon P. Vingron
ISBN: 978-3-642-27656-9
Springer Heidelberg Dordrecht London New York
2012  publish

Part I CombinationalCircuits
1 Logic Variables and Events................................................ 3
1.1 Specifying a Circuit in Plain Prose .................................. 3
1.2 Analogue and Binary Timing Diagrams ............................ 4
1.3 Events Graph and Events Table* .................................... 7
1.4 Logic Variables and Logic Formulas*............................... 9
1.5 Drawing the Logic Circuit ........................................... 11
2 Switching Devices........................................................... 13
2.1 Pneumatic Valves..................................................... 13
2.2 Electric Relays........................................................ 17
2.3 CMOS Transistors.................................................... 22
3 Elementary Logic Functions .............................................. 27
3.1 Logic Functions ...................................................... 27
3.2 Basic Gates ........................................................... 30
3.3 Using AND, OR and NOT........................................... 33
3.4 Basic Laws............................................................ 34
3.5 Single-VariableFormulas............................................ 35
3.6 Commutative and Associative Laws* ............................... 36
3.7 Distributive Laws* ................................................... 37
3.8 Generalised DeMorganTheorems................................... 39
4 Normal Forms............................................................... 41
4.1 Minterms and Maxterms............................................. 41
4.2 Canonical Normal Forms ............................................ 43
4.3 Using Canonical Normal Forms..................................... 44
4.4 ZhegalkinNormal Form ............................................. 46
4.5 Dual ZhegalkinNormal Form ....................................... 48
5 KarnaughMaps............................................................. 51
5.1 How to Draw a KarnaughMap ...................................... 51
5.2 KarnaughSet and ConjunctiveTerm................................ 53
5.3 Proving and DevelopingTheorems.................................. 57
5.4 Evaluating KarnaughMaps.......................................... 59
5.5 KarnaughTrees and Map-EnteredVariables........................ 63
6 Adjacency and Consensus ................................................. 67
6.1 Adjacent K-Sets and their Consensus*.............................. 67
6.2 Formalising Adjacency............................................... 70
6.3 Formalising Consensus .............................................. 72
6.4 When Is One K-Set a Subset of Another?........................... 73
7 AlgebraicMinimisation.................................................... 75
7.1 Finding the Full Cover*.............................................. 75
7.2 Finding Minimal Covers*............................................ 78
7.3 Minimisation Considering Don’t Cares*............................ 81
8 Design by Composition* ................................................... 85
8.1 The Basic Concept ................................................... 85
8.2 Catenation ............................................................ 86
8.3 Visualising the Composition Problem............................... 88
8.4 Choosing a Generic Function........................................ 89
8.5 Composing a Circuit: Example 1.................................... 91
8.6 Composing a Circuit: Example 2.................................... 95
8.7 Composing a Circuit: Example 3.................................... 95
Part II Latches
9 Basic Theory of Latches* .................................................. 99
9.1 What Is a Latch?...................................................... 99
9.2 The Memory Function ............................................... 101
9.3 IntroducingInclusions and Exclusions.............................. 104
9.4 Basic Memory Evaluation-Formulas................................ 106
9.5 Generalised Memory Evaluation-Formulas......................... 108
10 Designing Feedback Latches* ............................................. 111
10.1 Feedback Evaluation-Formulas...................................... 111
10.2 Design and MemorisationHazards.................................. 113
10.3 Delayed Feedback.................................................... 117
10.4 Pre-established Feedback ............................................ 120
10.5 Minimisation ......................................................... 122
11 Elementary Latches ........................................................ 125
11.1 Classification of ElementaryLatches................................ 125
11.2 Symbols for Elementary Latches*................................... 128
11.3 PredominantlyMemorisingLatches* ............................... 130
11.4 PredominantlySetting and Resetting* .............................. 131
11.5 Eccles-Jordan Latches—the Principle............................... 134
11.6 Eccles-Jordan Latches—TheirSymbols* ........................... 136
11.7 Standard Symbols for Latches....................................... 138
12 Latch Composition*........................................................ 141
12.1 Principle of Latch Composition ..................................... 142
12.2 D-Latch Designs...................................................... 146
12.3 PSR-Latches Using NAND or NOR-Gates ......................... 150
12.4 SynchronousLatch-Inputs........................................... 153
Part III Asynchronous Circuits
13 Word-RecognitionTree*................................................... 157
13.1 Priority-AND......................................................... 157
13.2 Two-Hand Safety Circuit ............................................ 161
13.3 D-Flipflop and T-Flipflop ............................................ 163
13.4 JK-Flipflop............................................................ 166
14 Huffman’sFlow Table...................................................... 169
14.1 Moore-TypeSequential Automaton ................................. 169
14.2 Primitive Flow-Table................................................. 172
14.3 Specifying Priority-AND Circuits................................... 173
14.4 Sampling and Synchronising ........................................ 175
14.5 Passed-Sample Problem.............................................. 178
14.6 ExpandedTwo-Hand Safety Problem............................... 182
14.7 From Flow Table to Events Graph................................... 184
15 State-Encoding by Iterative Catenation* ................................ 187
15.1 Catenation: From Moore to Mealy .................................. 187
15.2 Iterative Catenation................................................... 189
15.3 ExpandedPriority-AND ............................................. 190
15.4 Two-Hand Safety Circuits ........................................... 192
15.5 D-Latch and D-Flipflop .............................................. 193
15.6 Passed-Sample Circuit ............................................... 195
15.7 IncompletelySpecified Flow Tables................................. 199
16 Circuit Analysis............................................................. 203
16.1 Analysing a Circuit’s External Behaviour........................... 203
16.2 Formalistic Analysis of State Transitions ........................... 206
16.3 Realistic Analysis and Essential Hazards ........................... 208
16.4 Avoiding Essential Hazards.......................................... 214
17 State Reduction*............................................................ 217
17.1 MergingToward a Moore Flow Table............................... 218
17.2 MergingToward a Mealy Flow Table ............................... 220
17.3 MergingIncompletelySpecified Tables............................. 222
17.4 Mealy-Type Sequential Automaton ................................. 224
18 Verifying a Logic Design*.................................................. 227
18.1 End-Nodesand Their Event Graphs................................. 227
18.2 Verification Tree and Verification Graph............................ 229
18.3 Verification Table..................................................... 234
18.4 Verification Graph for the JK-Flipflop .............................. 237 1
8.5 Verification Graph for the D-Latch.................................. 238 1
8.6 Verification Graph for the D-Flipflop ............................... 239
Glossary ........................................................................... 245
Bibliography...................................................................... 251
Index............................................................................... 253