low power design

Avalon

Foreword Preface Acknowledgements References and Bibliography	Sect.1 - 2 Sect.1 - 3 Sect.1 - 4 Sect.1 - 6
Low-Power Links     Power Forward Initiative     Cadence Low-Power Links	Sect.1 - 9 Sect.1 - 10 Sect.1 - 10
CPF Terminology Glossary     Design Objects     CPF Objects	Sect.1 - 12 Sect.1 - 12 Sect.1 - 12
Special Library Cells for Power Management	Sect.1 - 14
Introduction to Low Power     Low Power Today     Power Management     Complete Low-Power RTL-to-GDSII Flow Using CPF     A Holistic Approach to Low-Power Intent     Verification of Low-Power Intent with CPF     Power Intent Validation     Low-Power Verification     CPF Verification Summary	Sect.1 - 16 Sect.1 - 16 Sect.1 - 18 Sect.1 - 31 Sect.1 - 37 Sect.1 - 40 Sect.1 - 40 Sect.1 - 42 Sect.1 - 57
Front-End Design with CPF     Architectural Exploration     Synthesis Low-Power Optimization     Automated Power Reduction in Synthesis     CPF-Powered Reduction in Synthesis     Simulation for Power Estimation     CPF Synthesis Summary	Sect.1 - 60 Sect.1 - 60 Sect.1 - 62 Sect.1 - 64 Sect.1 - 69 Sect.1 - 79 Sect.1 - 82
Power-Aware Design for Test (DFT)     Power Domain-Aware DFT     Power-Aware Test     CPF Test Summary	Sect.1 - 84 Sect.1 - 84 Sect.1 - 85 Sect.1 - 88
Low-Power Implementation with CPF     Introduction to Low-Power Implementation     Gate-Level Optimization in Power-Aware Physical Synthesis     Clock Gating in Power-Aware Physical Synthesis     Multi-Vth Optimization in Power-Aware Physical Synthesis     Multiple Supply Voltage (MSV) in Power-Aware Physical Synthesis     Power Shut-Off (PSO) in Power-Aware Physical Synthesis     Dynamic Voltage/Frequency Scaling (DVFS) Implementation     Substrate Biasing Implementation     Diffusion Biasing     CPF Implementation Summary	Sect.1 - 90 Sect.1 - 90 Sect.1 - 93 Sect.1 - 93 Sect.1 - 94 Sect.1 - 95 Sect.1 - 97 Sect.1 - 104 Sect.1 - 105 Sect.1 - 108 Sect.1 - 109
ARC Energy PRO: Technology for Active Power Management     Overview of ARC Energy PRO     The Power Struggle     Designing Low-Power Solutions     Project Subsystem: ARC CPU with Co-Processor     Conclusion	Sect.2 - 2 Sect.2 - 2 Sect.2 - 2 Sect.2 - 2 Sect.2 - 5 Sect.2 - 8
NEC Electronics: Integrating Power Awareness in SoC Design with CPF     NEC Electronics and CPF     Why Low Power?     Comprehensive Approach to Low Power     Example of Mobile Phone System SoC     NEC Electronics CPF Proof-Point Project: NEC-PPP     Summary	Sect.3 - 2 Sect.3 - 3 Sect.3 - 4 Sect.3 - 6 Sect.3 - 7 Sect.3 - 11 Sect.3 - 18
Fujitsu: CPF in the Low-Power Design Reference Flow     Fujitsu and CPF     Low-Power Design Techniques Used by Fujitsu     Low-Power Test Chip Developed with CPF     Low-Power Design Flow with CPF     Review of Low-Power Test Chip Design     Fujitsu Reference Design Flow 3.0: Low Power with CPF     Fujitsu's CPF Low-Power RDF Methodology     Summary	Sect.4 - 2 Sect.4 - 4 Sect.4 - 5 Sect.4 - 6 Sect.4 - 7 Sect.4 - 8 Sect.4 - 9 Sect.4 -14 Sect.4 -14
NXP User Experience: Complex SoC Implementation with CPF     Low Power is Critical to NXP     CPF in Action on a Complex SoC Platform     Power Network Intent     Hierarchical Support for IP and Design Reuse     Scalable Implementation     DFT Impact     CPF-Based Results	Sect.5 - 2 Sect.5 - 4 Sect.5 - 7 Sect.5 - 8 Sect.5 - 12 Sect.5 - 13 Sect.5 - 17 Sect.5 - 18
Freescale: Wireless Low-Power Design and Verification with CPF     Business Implications of Power     Wireless Carriers and Power     Phone Power and Energy     Active Power Challenge and Design Techniques     Low-Power Design Methodology and CPF     Mobile Application Power Reduction Results     Summary	Sect.6 - 2 Sect.6 - 2 Sect.6 - 3 Sect.6 - 3 Sect.6 - 10 Sect.6 - 11 Sect.6 - 14 Sect.6 - 15
TSMC: Advanced Design for Low Power at 65nm and Below     TSMC 65nm Low-Power Process     Low-Power Design Techniques     CPF: The Low-Power Standard     The TSMC Proof-Point Project     CPF-Based TSMC Reference Flow 9.0.     TSMC Low-Power Library: CPF Compliant     Summary	Sect.7 - 2 Sect.7 - 3 Sect.7 - 3 Sect.7 - 3 Sect.7 - 5 Sect.7 -9 Sect.7 - 20 Sect.7 - 21
ARM: 1176 IEM Reference Methodology     Introduction     ARM-Cadence Implementation Reference Methodologies     ARM1176 Processor     ARM1176JZF-S Low-Power Reference Methodology     Conclusion	Sect.8 - 2 Sect.8 - 2 Sect.8 - 3 Sect.8 - 4 Sect.8 - 8 Sect.8 - 26
Faraday: CPF-Based Low-Power Design Methodology for Platform-Based SoCs     Faraday Design Services and Low-Power Design     Introduction     Faraday CPF Flow     Faraday So Compiler CPF-Enabled Platform-Based Design for Low-Power     A Low-Power Platform-Based Design Example     Faraday CPF Low-Power SoCompiler Design Methodology Summary	Sect.9 - 2 Sect.9 - 2 Sect.9 - 3 Sect.9 - 4 Sect.9 - 6 Sect.9 - 17 Sect.9 - 23
Sequence Design: Early Power Analysis with CPF     Design for Power     Nano CPU Design Overview     Conclusions	Sect.10 - 2 Sect.10 - 2 Sect.10 - 7 Sect.10 - 11
ARM Cortex iRM: CPF-Driven Low-Power Functionality in a High-Performance Design Flow     ARM and Cadence Collaboration     iRM Flow Setups: Adding Low-Power Functionality to a High-Performance Design Flow     Other Low-Power Functionality Additions to a High-Performance Design Flow     Conclusions and Availability of ARM/Cadence iRMs	Sect.11 - 2 Sect.11 - 2 Sect.11 - 5 Sect.11 - 16 Sect.11 - 19
When Do You Know You Have Saved Enough Power?     Impact of Low-Power Design     Power Dissipation     Static Power Optimization     Static Power Optimization     Dynamic Power Optimization     ARM Intelligent Energy Manager™(IEM)     Power Savings in Multicore Processors     Conclusions	Sect.12 - 2 Sect.12 - 2 Sect.12 - 3 Sect.12 - 3 Sect.12 - 5 Sect.12 - 7 Sect.12 - 11 Sect.12 - 14 Sect.12 - 16
AMD: Power Gating in a High-Performance GPU     AMD and Low Power     Front-End Low-Power Logical Design/Verification Flow and Methodology     Back-End Low-Power Physical Design/Verification Flow and Methodology     CPF and Results     Summary of Results	Sect.13 - 2 Sect.13 - 2 Sect.13 - 9 Sect.13 - 14 Sect.13 - 19 Sect.13 - 22
ARM 1176-JZFS CPU-Based Low-Power Subsystem: Methodology to Reduce Electrical and Functional Failure in a Low-Power Design     Abstract     Overview of Ulterior Project     Ulterior Implementation     Assembly and Packaging     Ulterior Implementation Results	Sect.14 - 2 Sect.14 - 2 Sect.14 - 2 Sect.14 - 11 Sect.14 - 22 Sect.14 - 23
Sonics: CPF Flow for Highly-Configurable On-Chip Network IP     Overview     Sonic Power Management Features     CPF Generation and Automation     Sample SoC Design     Sonics CPF-based Low-Power Flow     Low-Power Reference Flow and Tools     Conclusion	Sect.15 - 2 Sect.15 - 2 Sect.15 - 4 Sect.15 - 5 Sect.15 - 6 Sect.15 - 7 Sect.15 - 12 Sect.15 - 14
Virage Logic: Minimizing Design Complexity with Power-Optimized Physical IP     Virage Logic�s IP Portfolio     Economics of Battery Life     Economics of IC Cooling     Low Power Design Solutions     Virage Logic Power-Optimization Kit: Standard Cell Set     Standard Cell in the Power Optimization Kit     Using Library CPF for Level Shifters, Retention Flops and Power Switches     40nm SiWare Memory Performance/Power Tradeoffs for Bank and Column Mux     Summary

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