Xilinx ISE 复位信号在Map时出错？

naijgnay

求助各位大神！!工程中所有模块使用rs_n复位信号，复位通过外部按键控制，通过了综合和翻译，但是在映射时报错，好像是把我的复位信号rs_n当做时钟信号了，错误如下：
ERRORlace:1398 - A clock IOB / BUFGCTRL clock component pair have been found
   that are not placed at an optimal clock IOB / BUFGCTRL site pair. The clock
   IOB component <rs_n> is placed at site <41>. The corresponding BUFGCTRL
   component <rs_n_IBUF_BUFG> is placed at site <BUFGCTRL_X0Y11>. The clock IO
   can use the fast path between the IOB and the Clock Buffer if the IOB is
   placed on a Clock Capable IOB site that has dedicated fast path to BUFGCTRL
   sites in its half of the device (TOP or BOTTOM). You may want to analyze why
   this problem exists and correct it. If this sub optimal condition is
   acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint
   in the .ucf file to demote this message to a WARNING and allow your design to
   continue. However, the use of this override is highly discouraged as it may
   lead to very poor timing results. It is recommended that this error condition
   be corrected in the design. A list of all the COMP.PINs used in this clock
   placement rule is listed below. These examples can be used directly in the
   .ucf file to override this clock rule.
   < NET "rs_n" CLOCK_DEDICATED_ROUTE = FALSE; >
ERRORack:1654 - The timing-driven placement phase encountered an error.
请问是什么地方出错了呢？

harry_hust

回复 3# naijgnay


   你使用的FPGA型号对应的datasheet，一般FPGA都会有一个bank都是全局管脚，这个bank通常用作时钟等全局信号输入。

harry_hust

回复 1# naijgnay


   这种情况属于PCB设计时没有将复位信号接到全局管脚上，解决方法一是看是否有按键接在全局管脚上，可以用该按键作为复位信号（具体请看FPGA的datasheet），二是不用全局管脚，在ucf文件里面添加< NET "rs_n" CLOCK_DEDICATED_ROUTE = FALSE; >括号内的约束命令，但这可能会导致时序问题。

naijgnay

回复 2# harry_hust

多谢回复！请问是在FPGA的哪个datasheet上有说明哪个管脚是不是全局管脚呢？或者在ISE IO Pin Planning的软件中全局管脚用什么标识的？

acgoal

回复 4# naijgnay


   很久之前看过，记得是管脚名称上有标志的，一般的管脚叫IO_XxxYxx什么的，全局管脚名称后面带MRCC还是SRCC的，这两者也有区别，你可以另查一下。

naijgnay

回复 5# acgoal
好的，多谢版主