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[招聘] 招聘后端工程师

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发表于 2015-4-24 10:33:10 | 显示全部楼层 |阅读模式

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后端经理JD

公司因为高速发展,需要招聘后端设计经理/工程师一名。资历优秀的可以考虑高级经理。


- Perform physical design implementation,including floor planning, power grid design, place and route, clock treesynthesis, timing closure, power/signal integrity signoff, physicalverification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure and able to createthe GDSII for tape out - The candidate will have the opportunity to work onmany varieties of challenging design projects.

- Ability to handle large sized designimplementation tasks alone


Requirements:



-Must have hands on physical design and verification experience in the past twoyears in large scale ASIC chip physical design, 28 nm experience is preferred

- BS degree with 2+ years of applicableexperience, MS degree with 4+ years of applicable experience in electricalengineering, microelectronics.

- Experienced with ASIC design flow,hierarchical physical design strategies, and methodologies and understand deepsub-micron technology issues. Solid knowledge on LP Design, static timinganalysis, EM/IR-Drop/crosstalk analysis, formal verification, physicalverification, DFM. Successful track records of taping out complex, 65/40/28 nmSOC chips.

- Self-motivated, able to workindependently or as a team player, customer focus, accountability, effectivecommunicator, able to coach and provide feedback and develop others

- Excellent verbal and writtencommunication skills in English and project management skills

-Self-initiative, quick learner, eager to learn new technologies

- Good at multi-tasking and prioritysetting


感兴趣可联系我(cissy_pq@163.com)(彭小姐)

发表于 2015-4-24 11:01:54 | 显示全部楼层
高速发展, 赞
发表于 2015-4-24 11:50:24 | 显示全部楼层
MS 4年就是mgr了, 要求不算高,
 楼主| 发表于 2015-4-24 13:27:21 | 显示全部楼层
回复 3# icfbicfb


   有需要可联系我哦
发表于 2015-4-29 14:29:09 | 显示全部楼层
唉,么有做过28n的
发表于 2018-3-19 19:41:30 | 显示全部楼层
7nm工艺
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