急招

Cissy_pq

后端工程师：

岗位职责：
Responsibilities:
1. Responsible for developing digital designswith emphasis on backend, including Floor-plan, power planning, Place, CTS andRoute.

2. Work with Front-end designers to optimizetiming/area/power of the design implementation and perform static timinganalysis.
3. Optimization and Verification of layout fortape-out (including RC extraction, ECO, DRC, LVS).
4. Power IR drop analysis and optimization, areaand parasitic layout optimization, chip size optimization.
5. Static Timing analysis (Prime Time or ETS)and setup/hold fix.
7. Generation of fill structures according totechnology requirements.
任职资格：
Requirements:
1. 3+ years experience in backend design flowwith proven SOC tape-out experience.
2. Experienced in Synopsys/Cadence automaticallyphysical implementation tools and flows (IC-Compiler/ Astro / SOC-Encounter/Milky-way/ Star-RCX) is a plus.
3. Experience with one or more scriptinglanguages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.
4. Experience and knowledge about FE design (RTLcode, flow) and verification is a plus.
5. Good analytical and debugging skills.
6. Good command of English.

感兴趣可联系我（cissy_pq@163.com）

icfbicfb

这种人往往是很多企业最需要的，

ksj116

职位地点。。。

Cissy_pq

回复 3# ksj116


   职位是后端工程师，如果资历好的话可以是后端工程师的leader。地点是张江或者漕河泾

Cissy_pq

回复 2# icfbicfb


   是的呢，比较着急