使用Xilinx的FPGA开发板中DCM的问题的解决方法

liping09003

[p=193, 2, left]在使用

[p=193, 2, left]Xilinx

[p=193, 2, left]的

[p=193, 2, left]FPGA

[p=193, 2, left]开发板时，在设计时内部需要使用不同的时钟频率，

[p=193, 2, left]可能会需要一个甚至多个

[p=193, 2, left]DCM

[p=193, 2, left]把所需要的时钟频率倍频或者是分频出来，

[p=193, 2, left]在编

[p=193, 2, left]译、综合、映射、布局布线的过程中会出现下列问题（

[p=193, 2, left]ERROR

[p=193, 2, left]）：

[p=207, 2, left]ERRORlace:1012 - A clock IOB / DCM component pair have been found that are

[p=207, 2, left]not placed at an optimal clock IOB / DCM

[p=207, 2, left]site

[p=207, 2, left]pair.

[p=207, 2, left]The

[p=207, 2, left]clock

[p=207, 2, left]component

[p=207, 2, left]<u1/u0/DCM_SP_INST>

[p=207, 2, left]is

[p=207, 2, left]placed

[p=207, 2, left]at

[p=207, 2, left]site

[p=207, 2, left]<DCM_X0Y1>.

[p=207, 2, left]The clock IO/DCM site can be

[p=207, 2, left]paired if they are placed/locked in the same quadrant.

[p=207, 2, left]The IO component <clk>

[p=207, 2, left]is placed at site <32>.

[p=207, 2, left]This will

[p=207, 2, left]not allow the use of the fast path between the IO and the Clock buffer. If this sub

[p=207, 2, left]optimal condition is acceptable

[p=207, 2, left]for

[p=207, 2, left]this

[p=207, 2, left]design,

[p=207, 2, left]you

[p=207, 2, left]may

[p=207, 2, left]use

[p=207, 2, left]the

[p=207, 2, left]CLOCK_DEDICATED_ROUTE

[p=207, 2, left]constraint

[p=207, 2, left]in

[p=207, 2, left]the .ucf file to demote this message to a

[p=207, 2, left]WARNING and allow your design to continue. However, the use of this override

[p=207, 2, left]is highly discouraged as it may lead to

[p=207, 2, left]very poor timing results. It is recommended that this error condition be corrected

[p=207, 2, left]in the design. A list of all the

[p=207, 2, left]COMP.PINs used in this clock placement rule is listed below. These examples can

[p=207, 2, left]be used directly in the .ucf file to

[p=207, 2, left]override this clock rule.

[p=207, 2, left]< NET "clk" CLOCK_DEDICATED_ROUTE = FALSE; >

[p=207, 2, left]<

[p=207, 2, left]PIN

[p=207, 2, left]"u1/u0/DCM_SP_INST.CLKIN"

[p=207, 2, left]CLOCK_DEDICATED_ROUTE

[p=207, 2, left]=

[p=207, 2, left]FALSE; >

[p=193, 2, left]在

[p=193, 2, left]UCF

[p=193, 2, left]里加入上面两句的话，

[p=193, 2, left]clk

[p=193, 2, left]和

[p=193, 2, left]clkin

[p=193, 2, left]走的不是全局时钟线：

[p=207, 2, left]< NET "clk" CLOCK_DEDICATED_ROUTE = FALSE; >

[p=207, 2, left]<

[p=207, 2, left]PIN

[p=207, 2, left]"u1/u0/DCM_SP_INST.CLKIN"

[p=207, 2, left]CLOCK_DEDICATED_ROUTE

[p=207, 2, left]=

[p=207, 2, left]FALSE; >

greenpine

这个有可能是bufg的问题
你的帖子格式有问题，看起来费劲

yurunsun

DJNHDFJNFXC DRTHJDRSJTSRJDFJ

yurunsun

JNDFJHS DHVSEHRH

polozpt

回复 1# liping09003

应该是时钟没有经过全局时钟管脚进入fpga，在ucf中约束