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Job Spec IC design- Automatic Placement and Routing(APR)Engineer 1 Be responsible for advanced chip implementation flow development,chip PPA boost, and support headquarter advanced technology for EDA router engagement 2 ASIC block-level implementation and/or full-chip integration projects 3 Develop IC design methodology Requirement 1 MS or PHD in CS,EE related field with experience in APR,physical verification,chip implementation, or CAD algorithm. 2 Expert in ASIC RTL-to-GDS design flow 3 Solid skill sets of Cadence/Synsopsys/Mentor EDA tools 4 Experience with TSMC 40nm technology 5 Experience in implementation signoff 6 Proven record in production tapeouts 7 Experience in tapeout with multi-million gates count SOC design. 28nm/40nm design experience is a plus 8 Capable of executing timing budgeting,synthesis,P&R,CTS, timing closure,DFT,physical verification,DFM and spice simulations. 9 Experience in CAD methodology and problem solving skill 10 Familiar with Verilog,Perl/Tcl and C/C++ 11 Good communiction in English 薪资面议 简历投递邮箱：yliug@tsmc.com | 
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发表于 2015-1-7 13:22:05
发表于 2015-1-7 18:19:17
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