|

楼主 |
发表于 2014-11-17 11:13:13
|
显示全部楼层
回复 2# icfbicfb
版主大人,您终于来了,可是我写着那句话的啊,是不是因为我还写了其他的,您帮我看看,这是我的 Link_lib.path文件中的:
define_name_rules rule0 -restricted "\!\@\#\$\%\^\&\*\(\)\/\-\"\{\}" -case_insensitive -map {{{"%s_%d","%s[%d]"}}} -type net -target_bus_naming_style {%s[%d]}
define_name_rules rule1 -restricted "\!\@\#\$\%\^\&\*\(\)\/\-\"\{\}" -case_insensitive -map {{{"%s_%d","%s[%d]"}}} -type cell -target_bus_naming_style {%s[%d]}
define_name_rules rule2 -restricted "\!\@\#\$\%\^\&\*\(\)\/\-\"\{\}" -case_insensitive -map {{{"%s_%d","%s[%d]"}}} -type port -target_bus_naming_style {%s[%d]}
define_name_rules rule3 -remove_port_bus
define_name_rules rule4 -case_insensitive -map {{{"_reg_%d","_reg[%d]"}}}
这是我的run.dc.tcl文件中的:
set bus_dimension_separator_style "[]"
#set bus_naming_style {%s_%d}
set bus_naming_style {%s[%d]}
change_names -rules verilog -hier
change_names -rule rule0 -hierarchy
change_names -rule rule1 -hierarchy
change_names -rule rule2 -hierarchy
change_names -rule rule3 -hierarchy
change_names -rule rule4 -hierarchy
write -format verilog -hierarchy -output ./report/$module.net
结果就变成了:
module test ( clk, \din[1] , \din[0] , rst_n, \q[1] , \q[0] );
input clk, \din[1] , \din[0] , rst_n;
output \q[1] , \q[0] ;
HDR_DRNQ_1 q_reg_1_ ( .D(\din[0] ), .CK(clk), .RDN(rst_n), .Q(\q[1] ) );
HDR_DRNQ_1 q_reg_0_ ( .D(\din[1] ), .CK(clk), .RDN(rst_n), .Q(\q[0] ) );
endmodule |
|