New Synplify 2014.03-1 Available Now!

jerryaaaa

Faster Runtime, Higher Performance, Enhanced Quality of Results and Improved Design Diagnostics Accelerate Innovation


How to Use the New Features:

    1.Faster incremental compilation capability and structural Verilog “pass through” flow for improved runtime and design stability

    2.Faster “High QoR” flow for large Xilinx® Ultrascale and Altera® Arria® 10 devices

    3.Improved timing QoR and timing correlation for Xilinx and Altera devices, especially those that include DSPs
   
    4.Easier Vivado design flow setup and QoR, via automatic creation of FDC constraint files

    5.Design debug and prototyping automation improvements including Verilog Force/Bind capability
   
    6.Early resource estimation and control for clocks, memories and DSPs

    7.DSP block generator for CORDIC and MATH functions for greater DSP design productivity

    8.Enhanced “safe FSM” capability that now allows user-defined state encoding



    Download this release NOW! from the SolvNet Downloads Center, if you are a current Synplify user with a valid Synopsys’ SolvNet ID.

    Not currently a Synplify user? Request a free evaluation copy of Synplify Premier Now!

zjwumei

支持一下，顶楼主

lihaiz

好像运行不起来，不知道神马情况

paul21st

goood

jlqsczw_2007

Faster Runtime, Higher Performance, Enhanced Quality of Results and Improved Design Diagnostics Acce ...
jerryaaaa 发表于 2014-5-20 23:53

                               
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    有网盘链接吗？

pumpkin

waitting...

snk88

回复 3# lihaiz


   上传，，，

jerryaaaa

安装一个软件，就像是一时兴起，买了本新书，装完之后用与不用，如同买的新书读与不读一样。

   一个软件是设计者想说的法，法为因缘生，因为一方面有人在求法，故有新版本的产生，又因为以前说的法不能穷尽于用，故有补丁程序的发布。

   然则法无定法，因众生病而说法，众生随欢喜而择其法，而后用心演练其法。

   当心中有定处，方知此法非法，而无法。

                                          一位EDA 软件的爱好者
                                                  2014.5.22

jerryaaaa

uploading...

jerryaaaa

uploading...