有人看过uvm_ref_flow_1.1里的uart组件么？

oscillator_cn1

各位：      关于uart的采样频率，我有点不大明白。sample_clk是对interface上的时钟进行计数，等于{cfg.baud_rate_div,cfg.baud_rate_gen}的时候开始采样，那我不大清楚，验证的时候该依据什么来配置这两个值。而且，不是说异步的嘛，为什么rx和tx都用同样的配置。
      我知道我这样说没有语境，因此，贴上rx_driver、transfer和interface的代码。
dirver:

1. `ifndef UART_RX_DRIVER
   
2. `define UART_RX_DRIVER
   
3. 
   
4. class uart_rx_driver extends uvm_driver #(uart_frame) ;
   
5. 
   
6.   // The virtual interface used to drive and view HDL signals.
   
7.   virtual interface uart_if vif;
   
8. 
   
9.   // handle to  a cfg class
   
10.   uart_config cfg;
    
11. 
    
12.   bit sample_clk;
    
13.   bit [15:0] ua_brgr;
    
14.   bit [7:0] ua_bdiv;
    
15.   int num_of_bits_sent;
    
16.   int num_frames_sent;
    
17. 
    
18.   // Provide implementations of virtual methods such as get_type_name and create
    
19.   `uvm_component_utils_begin(uart_rx_driver)
    
20.     `uvm_field_object(cfg, UVM_DEFAULT | UVM_REFERENCE)
    
21.     `uvm_field_int(ua_brgr, UVM_DEFAULT + UVM_NOPRINT)
    
22.     `uvm_field_int(ua_bdiv, UVM_DEFAULT + UVM_NOPRINT)
    
23.   `uvm_component_utils_end
    
24. 
    
25.   // Constructor - required UVM syntax
    
26.   function new(string name, uvm_component parent);
    
27.     super.new(name,parent);
    
28.   endfunction
    
29. 
    
30.   // Additional class methods
    
31.   extern virtual function void build_phase(uvm_phase phase);
    
32.   extern virtual function void connect_phase(uvm_phase phase);
    
33.   extern virtual task run_phase(uvm_phase phase);
    
34.   extern virtual task reset();
    
35.   extern virtual task get_and_drive();
    
36.   extern virtual task gen_sample_rate(ref bit [15:0] ua_brgr, ref bit sample_clk);
    
37.   extern virtual task send_rx_frame(input uart_frame frame);
    
38.   extern virtual function void report_phase(uvm_phase phase);
    
39.   
    
40. endclass : uart_rx_driver
    
41. 
    
42. // UVM build_phase
    
43. function void uart_rx_driver::build_phase(uvm_phase phase);
    
44.     super.build_phase(phase);
    
45.     if(cfg == null)
    
46.       if (!uvm_config_db#(uart_config)::get(this, "", "cfg", cfg))
    
47.        `uvm_error("NOCONFIG", "uart_config not set for this component")
    
48. endfunction : build_phase
    
49. 
    
50. //UVM connect_phase
    
51. function void uart_rx_driver::connect_phase(uvm_phase phase);
    
52.   super.connect_phase(phase);
    
53.   if (!uvm_config_db#(virtual uart_if)::get(this, "", "vif", vif))
    
54.    `uvm_error("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})
    
55. endfunction : connect_phase
    
56. 
    
57. //UVM run_phase
    
58. task uart_rx_driver::run_phase(uvm_phase phase);
    
59.   fork
    
60.     get_and_drive();
    
61.     gen_sample_rate(ua_brgr, sample_clk);
    
62.   join
    
63. endtask : run_phase
    
64. 
    
65. // reset
    
66. task uart_rx_driver::reset();
    
67.   @(negedge vif.reset);
    
68.   `uvm_info(get_type_name(), "Reset Asserted", UVM_MEDIUM)
    
69.    vif.rxd = 1;        //Receive Data
    
70.    vif.cts_n = 0;      //Clear to Send
    
71.    vif.dsr_n = 0;      //Data Set Ready
    
72.    vif.ri_n = 0;       //Ring Indicator
    
73.    vif.baud_clk = 0;   //Baud Clk - NOT USED
    
74. endtask : reset
    
75. 
    
76. //  get_and drive
    
77. task uart_rx_driver::get_and_drive();
    
78.   while (1) begin
    
79.     reset();
    
80.     fork
    
81.       @(negedge vif.reset)
    
82.         `uvm_info(get_type_name(), "Reset asserted", UVM_LOW)
    
83.     begin
    
84.       forever begin
    
85.         @(posedge vif.clock iff (vif.reset))
    
86.         seq_item_port.get_next_item(req);
    
87.         send_rx_frame(req);
    
88.         seq_item_port.item_done();
    
89.       end
    
90.     end
    
91.     join_any
    
92.     disable fork;
    
93.     //If we are in the middle of a transfer, need to end the rx. Also,
    
94.     //do any reset cleanup here. The only way we got to this point is via
    
95.     //a reset.
    
96.     if(req.is_active()) this.end_tr(req);
    
97.   end
    
98. endtask : get_and_drive
    
99. 
    
100. task uart_rx_driver::gen_sample_rate(ref bit [15:0] ua_brgr, ref bit sample_clk);
     
101.   forever begin
     
102.     @(posedge vif.clock);
     
103.     if (!vif.reset) begin
     
104.       ua_brgr = 0;
     
105.       sample_clk = 0;
     
106.     end else begin
     
107.       if (ua_brgr == ({cfg.baud_rate_div, cfg.baud_rate_gen})) begin
     
108.         ua_brgr = 0;
     
109.         sample_clk = 1;
     
110.       end else begin
     
111.         sample_clk = 0;
     
112.         ua_brgr++;
     
113.       end
     
114.     end
     
115.   end
     
116. endtask : gen_sample_rate
     
117. 
     
118. // -------------------
     
119. // send_rx_frame
     
120. // -------------------
     
121. task uart_rx_driver::send_rx_frame(input uart_frame frame);
     
122.   bit [7:0] payload_byte;
     
123.   num_of_bits_sent = 0;
     
124. 
     
125.   `uvm_info(get_type_name(),
     
126.             $psprintf("Driver Sending RX Frame...\n%s", frame.sprint()),
     
127.             UVM_HIGH)
     
128. 
     
129.   repeat (frame.transmit_delay)
     
130.     @(posedge vif.clock);
     
131.   void'(this.begin_tr(frame));
     
132.    
     
133.   wait((!cfg.rts_en)||(!vif.cts_n));
     
134.   `uvm_info(get_type_name(), "Driver - Modem RTS or CTS asserted", UVM_HIGH)
     
135. 
     
136.   while (num_of_bits_sent <= (1 + cfg.char_len_val + cfg.parity_en + cfg.nbstop)) begin
     
137.     @(posedge vif.clock);
     
138.     #1;
     
139.     if (sample_clk) begin
     
140.       if (num_of_bits_sent == 0) begin
     
141.         // Start sending rx_frame with "start bit"
     
142.         vif.rxd = frame.start_bit;
     
143.         `uvm_info(get_type_name(),
     
144.                   $psprintf("Driver Sending Frame SOP: %b", frame.start_bit),
     
145.                   UVM_HIGH)
     
146.       end
     
147.       if ((num_of_bits_sent > 0) && (num_of_bits_sent < (1 + cfg.char_len_val))) begin
     
148.         // sending "data bits"
     
149.         payload_byte = frame.payload[num_of_bits_sent-1] ;
     
150.         vif.rxd = frame.payload[num_of_bits_sent-1];
     
151.         `uvm_info(get_type_name(),
     
152.              $psprintf("Driver Sending Frame data bit number:%0d value:'b%b",
     
153.              (num_of_bits_sent-1), payload_byte), UVM_HIGH)
     
154.       end
     
155.       if ((num_of_bits_sent == (1 + cfg.char_len_val)) && (cfg.parity_en)) begin
     
156.         // sending "parity bit" if parity is enabled
     
157.         vif.rxd = frame.calc_parity(cfg.char_len_val, cfg.parity_mode);
     
158.         `uvm_info(get_type_name(),
     
159.              $psprintf("Driver Sending Frame Parity bit:'b%b",
     
160.              frame.calc_parity(cfg.char_len_val, cfg.parity_mode)), UVM_HIGH)
     
161.       end
     
162.       if (num_of_bits_sent == (1 + cfg.char_len_val + cfg.parity_en)) begin
     
163.         // sending "stop/error bits"
     
164.         for (int i = 0; i < cfg.nbstop; i++) begin
     
165.           `uvm_info(get_type_name(),
     
166.                $psprintf("Driver Sending Frame Stop bit:'b%b",
     
167.                frame.stop_bits[i]), UVM_HIGH)
     
168.           wait (sample_clk);
     
169.           if (frame.error_bits[i]) begin
     
170.             vif.rxd = 0;
     
171.             `uvm_info(get_type_name(),
     
172.                  $psprintf("Driver intensionally corrupting Stop bit since error_bits['b%b] is 'b%b", i, frame.error_bits[i]),
     
173.                  UVM_HIGH)
     
174.           end else
     
175.           vif.rxd = frame.stop_bits[i];
     
176.           num_of_bits_sent++;
     
177.           wait (!sample_clk);
     
178.         end
     
179.       end
     
180.     num_of_bits_sent++;
     
181.     wait (!sample_clk);
     
182.     end
     
183.   end
     
184.   
     
185.   num_frames_sent++;
     
186.   `uvm_info(get_type_name(),
     
187.        $psprintf("Frame **%0d** Sent...", num_frames_sent), UVM_MEDIUM)
     
188.   wait (sample_clk);
     
189.   vif.rxd = 1;
     
190. 
     
191.   `uvm_info(get_type_name(), "Frame complete...", UVM_MEDIUM)
     
192.   this.end_tr(frame);
     
193.    
     
194. endtask : send_rx_frame
     
195. 
     
196. //UVM report_phase
     
197. function void uart_rx_driver::report_phase(uvm_phase phase);
     
198.   `uvm_info(get_type_name(),
     
199.        $psprintf("UART Frames Sent:%0d", num_frames_sent),
     
200.        UVM_LOW )
     
201. endfunction : report_phase
     
202. 
     
203. `endif // UART_RX_DRIVER
     

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transfer:

1. `ifndef UART_FRAME_SVH
   
2. `define UART_FRAME_SVH
   
3. 
   
4. // Parity Type Control knob
   
5. typedef enum bit {GOOD_PARITY, BAD_PARITY} parity_e;
   
6. 
   
7. class uart_frame extends uvm_sequence_item;  //lab1_note1
   
8.   // UART Frame
   
9.   rand bit start_bit;
   
10.   rand bit [7:0] payload;
    
11.   bit parity;
    
12.   rand bit [1:0] stop_bits;
    
13.   rand bit [3:0] error_bits;
    
14. 
    
15.   // Control Knobs
    
16.   rand parity_e parity_type;
    
17.   rand int transmit_delay;
    
18. 
    
19.   // Default constraints  //lab1_note2
    
20.   constraint default_txmit_delay {transmit_delay >= 0; transmit_delay < 20;}
    
21.   constraint default_start_bit { start_bit == 1'b0;}
    
22.   constraint default_stop_bits { stop_bits == 2'b11;}
    
23.   constraint default_parity_type { parity_type==GOOD_PARITY;}
    
24.   constraint default_error_bits { error_bits == 4'b0000;}
    
25. 
    
26.   // These declarations implement the create() and get_type_name()
    
27.   // and enable automation of the uart_frame's fields     //lab1_note3
    
28.   `uvm_object_utils_begin(uart_frame)   
    
29.     `uvm_field_int(start_bit, UVM_DEFAULT)
    
30.     `uvm_field_int(payload, UVM_DEFAULT)  
    
31.     `uvm_field_int(parity, UVM_DEFAULT)  
    
32.     `uvm_field_int(stop_bits, UVM_DEFAULT)
    
33.     `uvm_field_int(error_bits, UVM_DEFAULT)
    
34.     `uvm_field_enum(parity_e,parity_type, UVM_DEFAULT + UVM_NOCOMPARE)
    
35.     `uvm_field_int(transmit_delay, UVM_DEFAULT + UVM_DEC + UVM_NOCOMPARE + UVM_NOCOPY)
    
36.   `uvm_object_utils_end
    
37. 
    
38.   // Constructor - required UVM syntax  //lab1_note4
    
39.   function new(string name = "uart_frame");
    
40.     super.new(name);
    
41.   endfunction
    
42.    
    
43.   // This method calculates the parity
    
44.   function bit calc_parity(int unsigned num_of_data_bits=8,
    
45.                            bit[1:0] ParityMode=0);
    
46.     bit temp_parity;
    
47. 
    
48.     if (num_of_data_bits == 6)
    
49.       temp_parity = ^payload[5:0];  
    
50.     else if (num_of_data_bits == 7)
    
51.       temp_parity = ^payload[6:0];  
    
52.     else
    
53.       temp_parity = ^payload;  
    
54. 
    
55.     case(ParityMode[0])
    
56.       0: temp_parity = ~temp_parity;
    
57.       1: temp_parity = temp_parity;
    
58.     endcase
    
59.     case(ParityMode[1])
    
60.       0: temp_parity = temp_parity;
    
61.       1: temp_parity = ~ParityMode[0];
    
62.     endcase
    
63.     if (parity_type == BAD_PARITY)
    
64.       calc_parity = ~temp_parity;
    
65.     else
    
66.       calc_parity = temp_parity;
    
67.   endfunction
    
68. 
    
69.   // Parity is calculated in the post_randomize() method   //lab1_note5
    
70.   function void post_randomize();
    
71.    parity = calc_parity();
    
72.   endfunction : post_randomize
    
73. 
    
74. endclass
    
75. 
    
76. `endif
    

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interface:

1. interface uart_if(input clock, reset);
   
2. 
   
3.   logic txd;    // Transmit Data
   
4.   logic rxd;    // Receive Data
   
5.   
   
6.   logic intrpt;  // Interrupt
   
7. 
   
8.   logic ri_n;    // ring indicator
   
9.   logic cts_n;   // clear to send
   
10.   logic dsr_n;   // data set ready
    
11.   logic rts_n;   // request to send
    
12.   logic dtr_n;   // data terminal ready
    
13.   logic dcd_n;   // data carrier detect
    
14. 
    
15.   logic baud_clk;  // Baud Rate Clock
    
16.   
    
17.   // Control flags
    
18.   bit                has_checks = 1;
    
19.   bit                has_coverage = 1;
    
20. 
    
21. /*  FIX TO USE CONCURRENT ASSERTIONS
    
22.   always @(posedge clock)
    
23.   begin
    
24.     // rxd must not be X or Z
    
25.     assertRxdUnknown:assert property (
    
26.                        disable iff(!has_checks || !reset)(!$isunknown(rxd)))
    
27.                        else
    
28.                          $error("ERR_UART001_Rxd_XZ\n Rxd went to X or Z");
    
29.   end
    
30. */
    
31. 
    
32. endinterface : uart_if
    

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allangoing

波特率是由你要测试的目的和dut决定的
异步并不是指tx和rx之间,指的是接收端和发送端所使用的时钟是否一样

oscillator_cn1

回复 2# allangoing

谢谢！也就是说我要试不同的配置以观察波特率？另外，不光是tx与rx采用一样的sample_clk，我看monitor那边也是这样弄的，driver是发送方，monitor是接收方对吧。

yongxin2011

回复 1# oscillator_cn1


  我目前也在看这个例子，有机会交流学习一下。q：466183347

hitshaoqi

回复 1# oscillator_cn1

看看