为什么我的stdcell在macro外面place呢？

zg8312 · 发表于 2013-9-5 17:23:55

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如图！那里也没有设置placement blockage！
刚开始的时候die area设置的和macro边框大小一样，floorplan的时候提示我空间不够！
试了好久才知道stdcell没有place进macro里面！
什么情况会是这样的呢？

陈涛 · 发表于 2013-9-6 07:39:01

U字型macro吧？没有定义overlap obs

half_honey · 发表于 2013-9-6 08:48:39

学到

zg8312 · 发表于 2013-9-6 08:59:10

回复 2# 陈涛

请问陈大！该如何定义，ana_top frame我是用gds使用astro工具生成的！谢谢！

zfx253 · 发表于 2013-9-6 10:44:15

用Milkways加
或者直接vi lef

zg8312 · 发表于 2013-9-6 10:49:44

回复 5# zfx253

Milkway什么功能呢？没有使用过呢！指点一下吧！谢谢拉！

zfx253 · 发表于 2013-9-6 11:46:44

synopsys的物理库编辑工具

zg8312 · 发表于 2013-9-6 15:41:34

#
# LEF OUT
# User Name : gzhang
# Date : Fri Sep 6 14:04:37 2013
#
VERSION 5.5 ;
NAMESCASESENSITIVE ON ;
BUSBITCHARS "[]" ;
DIVIDERCHAR "/" ;
MACRO ANA_TOP
CLASS BLOCK ;
SOURCE USER ;
ORIGIN 0 0 ;
SIZE 3002.95 BY 2427.83 ;
SYMMETRY X Y R90 ;
PIN PORT_PAD[8]
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2980.11 1650.51 2981.61 1652.01 ;
END
END PORT_PAD[8]
PIN PORT_PAD[7]
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2980.11 1653.51 2981.61 1655.01 ;
END
END PORT_PAD[7]
PIN PORT_PAD[6]
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2980.11 1656.51 2981.61 1658.01 ;
END
END PORT_PAD[6]
PIN PORT_PAD[5]
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2980.11 1659.51 2981.61 1661.01 ;
END
END PORT_PAD[5]
PIN PORT_PAD[4]
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2980.11 1662.51 2981.61 1664.01 ;
END
END PORT_PAD[4]
PIN PORT_PAD[3]
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2980.11 1665.51 2981.61 1667.01 ;
END
END PORT_PAD[3]
PIN PORT_PAD[2]
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2980.11 1668.51 2981.61 1670.01 ;
END
END PORT_PAD[2]
PIN PORT_PAD[1]
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2980.11 1671.51 2981.61 1673.01 ;
END
END PORT_PAD[1]
PIN TEST_MODE_PAD[1]
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2770.2 2338.575 2771.7 2340.075 ;
END
END TEST_MODE_PAD[1]
PIN VDD2_PAD
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2637.385 42.72 2638.885 44.22 ;
END
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PIN RST_N_PAD
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2770.2 2403.285 2771.7 2404.785 ;
END
END RST_N_PAD
PIN CLK_16M_PAD
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2854.53 2368.67 2856.03 2370.17 ;
END
END CLK_16M_PAD
PIN PORT_PAD[0]
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2980.11 1674.51 2981.61 1676.01 ;
END
END PORT_PAD[0]
PIN CE_PAD
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2957.975 1853.865 2959.475 1855.365 ;
END
END CE_PAD
PIN VSS2_PAD
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2957.975 1764.595 2959.475 1766.095 ;
END
END VSS2_PAD
PIN SCK_PAD
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2957.975 2022.355 2959.475 2023.855 ;
END
END SCK_PAD
PIN CSN_PAD
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2957.975 1941.585 2959.475 1943.085 ;
END
END CSN_PAD
PIN MISO_PAD
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2957.975 2191.55 2959.475 2193.05 ;
END
END MISO_PAD
PIN MOSI_PAD
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2957.975 2106.95 2959.475 2108.45 ;
END
END MOSI_PAD
PIN TX_EN_PAD
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2854.53 2385.975 2856.03 2387.475 ;
END
END TX_EN_PAD
PIN TX_EN_N_PAD
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2957.975 2275.055 2959.475 2276.555 ;
END
END TX_EN_N_PAD
PIN VDD1_PAD
USE SIGNAL ;
PORT
LAYER AT ;
RECT 454.565 2385.975 456.065 2387.475 ;
END
END VDD1_PAD
PIN IRQ0_N_PAD
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2770.2 2385.975 2771.7 2387.475 ;
END
END IRQ0_N_PAD
PIN XC2_PAD
USE SIGNAL ;
PORT
LAYER AT ;
RECT 225.64 2385.975 227.14 2387.475 ;
END
END XC2_PAD
PIN VSS1_PAD
USE SIGNAL ;
PORT
LAYER AT ;
RECT 358.41 2385.975 359.91 2387.475 ;
END
END VSS1_PAD
PIN VDD_PA_PAD
USE SIGNAL ;
PORT
LAYER AT ;
RECT 46.625 1937.485 48.125 1938.985 ;
END
END VDD_PA_PAD
PIN XC1_PAD
USE SIGNAL ;
PORT
LAYER AT ;
RECT 138.5 2385.975 140 2387.475 ;
END
END XC1_PAD
PIN ANT1_PAD
USE SIGNAL ;
PORT
LAYER AT ;
RECT 46.625 1709.275 48.125 1710.775 ;
END
END ANT1_PAD
PIN VSS3_PAD
USE SIGNAL ;
PORT
LAYER AT ;
RECT 46.625 1848.46 48.125 1849.96 ;
END
END VSS3_PAD
PIN ANT2_PAD
USE SIGNAL ;
PORT
LAYER AT ;
RECT 46.625 1541.08 48.125 1542.58 ;
END
END ANT2_PAD
PIN VDD3_PAD
USE SIGNAL ;
PORT
LAYER AT ;
RECT 46.625 242.805 48.125 244.305 ;
END
END VDD3_PAD
PIN VSS4_PAD
USE SIGNAL ;
PORT
LAYER AT ;
RECT 898.32 42.72 899.82 44.22 ;
END
END VSS4_PAD
PIN IREF_PAD
USE SIGNAL ;
PORT
LAYER AT ;
RECT 46.625 158.54 48.125 160.04 ;
END
END IREF_PAD
PIN DVDD_PAD
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2722.75 42.72 2724.25 44.22 ;
END
END DVDD_PAD
PIN SAR_ADC_TEST_POINT[3]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1472.205 833.145 1472.705 ;
END
END SAR_ADC_TEST_POINT[3]
PIN RX_RSSI_PWD
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 241.295 833.145 241.795 ;
END
END RX_RSSI_PWD
PIN RX_ADC_PWD
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 512.015 833.145 512.515 ;
END
END RX_ADC_PWD
PIN SAR_ADC_TEST_POINT[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1493.425 833.145 1493.925 ;
END
END SAR_ADC_TEST_POINT[0]
PIN RX_ADC_CS[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 334.345 833.145 334.845 ;
END
END RX_ADC_CS[0]
PIN RX_ADC_CS[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 335.345 833.145 335.845 ;
END
END RX_ADC_CS[1]
PIN SYN_BUF_BT
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1569.74 833.145 1570.24 ;
END
END SYN_BUF_BT
PIN RX_RSSI_LPF[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1509.325 833.145 1509.825 ;
END
END RX_RSSI_LPF[0]
PIN RX_RSSI_LPF[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1508.525 833.145 1509.025 ;
END
END RX_RSSI_LPF[1]
PIN TEMP_SEN_V2I
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1563.7 833.145 1564.2 ;
END
END TEMP_SEN_V2I
PIN RX_LNA_PWD
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1551.365 833.145 1551.865 ;
END
END RX_LNA_PWD
PIN RX_RSSI_ADC[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 242.895 833.145 243.395 ;
END
END RX_RSSI_ADC[0]
PIN RX_RSSI_ADC[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 243.695 833.145 244.195 ;
END
END RX_RSSI_ADC[1]
PIN RX_RSSI_ADC[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 244.495 833.145 244.995 ;
END
END RX_RSSI_ADC[2]
PIN RX_MIXER1_PWD
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1547.365 833.145 1547.865 ;
END
END RX_MIXER1_PWD
PIN RX_MIXER2_PWD
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1548.165 833.145 1548.665 ;
END
END RX_MIXER2_PWD
PIN TEMP_SEN_EN
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1564.5 833.145 1565 ;
END
END TEMP_SEN_EN
PIN RX_RF_MIXER_GAIN
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1548.965 833.145 1549.465 ;
END
END RX_RF_MIXER_GAIN
PIN RX_IF_MIXER_GAIN
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1549.765 833.145 1550.265 ;
END
END RX_IF_MIXER_GAIN
PIN RX_UNI_QUAD_GAIN[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1544.165 833.145 1544.665 ;
END
END RX_UNI_QUAD_GAIN[0]
PIN RX_UNI_QUAD_GAIN[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1544.965 833.145 1545.465 ;
END
END RX_UNI_QUAD_GAIN[1]
PIN RX_UNI_QUAD_GAIN[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1545.765 833.145 1546.265 ;
END
END RX_UNI_QUAD_GAIN[2]
PIN RX_PWD
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1550.565 833.145 1551.065 ;
END
END RX_PWD
PIN RX_ADC_OUT[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 336.345 833.145 336.845 ;
END
END RX_ADC_OUT[0]
PIN RX_ADC_OUT[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 337.345 833.145 337.845 ;
END
END RX_ADC_OUT[1]
PIN RX_ADC_OUT[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 338.345 833.145 338.845 ;
END
END RX_ADC_OUT[2]
PIN RX_ADC_OUT[3]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 339.345 833.145 339.845 ;
END
END RX_ADC_OUT[3]
PIN RX_ADC_OUT[4]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 340.345 833.145 340.845 ;
END
END RX_ADC_OUT[4]
PIN RX_ADC_OUT[5]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 341.345 833.145 341.845 ;
END
END RX_ADC_OUT[5]
PIN PORT_I[18]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1657.315 2968.28 1657.815 ;
END
END PORT_I[18]
PIN PORT_I[17]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1658.315 2968.28 1658.815 ;
END
END PORT_I[17]
PIN PORT_I[16]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1659.315 2968.28 1659.815 ;
END
END PORT_I[16]
PIN PORT_I[15]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1660.315 2968.28 1660.815 ;
END
END PORT_I[15]
PIN PORT_I[14]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1661.315 2968.28 1661.815 ;
END
END PORT_I[14]
PIN PORT_I[13]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1662.315 2968.28 1662.815 ;
END
END PORT_I[13]
PIN PORT_I[12]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1663.315 2968.28 1663.815 ;
END
END PORT_I[12]
PIN PORT_I[11]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1664.315 2968.28 1664.815 ;
END
END PORT_I[11]
PIN PORT_I[10]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1665.315 2968.28 1665.815 ;
END
END PORT_I[10]
PIN PORT_I[9]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1666.315 2968.28 1666.815 ;
END
END PORT_I[9]
PIN PORT_I[8]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1667.315 2968.28 1667.815 ;
END
END PORT_I[8]
PIN PORT_I[7]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1668.315 2968.28 1668.815 ;
END
END PORT_I[7]
PIN PORT_I[6]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1669.315 2968.28 1669.815 ;
END
END PORT_I[6]
PIN PORT_I[5]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1670.315 2968.28 1670.815 ;
END
END PORT_I[5]
PIN PORT_I[4]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1671.315 2968.28 1671.815 ;
END
END PORT_I[4]
PIN PORT_I[3]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1672.315 2968.28 1672.815 ;
END
END PORT_I[3]
PIN PORT_I[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1673.315 2968.28 1673.815 ;
END
END PORT_I[2]
PIN PORT_I[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1674.315 2968.28 1674.815 ;
END
END PORT_I[1]
PIN PORT_I[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1675.315 2968.28 1675.815 ;
END
END PORT_I[0]
PIN SYN_VT_ADJ
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2023.065 635.65 2023.565 ;
END
END SYN_VT_ADJ
PIN PORT_OEN[18]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1616.41 2968.28 1616.91 ;
END
END PORT_OEN[18]
PIN PORT_OEN[17]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1617.41 2968.28 1617.91 ;
END
END PORT_OEN[17]
PIN PORT_OEN[16]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1618.41 2968.28 1618.91 ;
END
END PORT_OEN[16]
PIN PORT_OEN[15]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1619.41 2968.28 1619.91 ;
END
END PORT_OEN[15]
PIN PORT_OEN[14]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1620.41 2968.28 1620.91 ;
END
END PORT_OEN[14]
PIN PORT_OEN[13]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1621.41 2968.28 1621.91 ;
END
END PORT_OEN[13]
PIN PORT_OEN[12]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1622.41 2968.28 1622.91 ;
END
END PORT_OEN[12]
PIN PORT_OEN[11]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1623.41 2968.28 1623.91 ;
END
END PORT_OEN[11]
PIN PORT_OEN[10]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1624.41 2968.28 1624.91 ;
END
END PORT_OEN[10]
PIN PORT_OEN[9]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1625.41 2968.28 1625.91 ;
END
END PORT_OEN[9]
PIN PORT_OEN[8]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1626.41 2968.28 1626.91 ;
END
END PORT_OEN[8]
PIN PORT_OEN[7]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1627.41 2968.28 1627.91 ;
END
END PORT_OEN[7]
PIN PORT_OEN[6]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1628.41 2968.28 1628.91 ;
END
END PORT_OEN[6]
PIN PORT_OEN[5]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1629.41 2968.28 1629.91 ;
END
END PORT_OEN[5]
PIN PORT_OEN[4]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1630.41 2968.28 1630.91 ;
END
END PORT_OEN[4]
PIN PORT_OEN[3]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1631.41 2968.28 1631.91 ;
END
END PORT_OEN[3]
PIN PORT_OEN[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1632.41 2968.28 1632.91 ;
END
END PORT_OEN[2]
PIN IRQ1_N_PAD
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2770.2 2369.885 2771.7 2371.385 ;
END
END IRQ1_N_PAD
PIN TEST_MODE_PAD[0]
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2770.2 2354.175 2771.7 2355.675 ;
END
END TEST_MODE_PAD[0]
PIN PORT_PAD[18]
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2980.11 1620.51 2981.61 1622.01 ;
END
END PORT_PAD[18]
PIN PORT_PAD[17]
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2980.11 1623.51 2981.61 1625.01 ;
END
END PORT_PAD[17]
PIN PORT_PAD[16]
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2980.11 1626.51 2981.61 1628.01 ;
END
END PORT_PAD[16]
PIN PORT_PAD[15]
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2980.11 1629.51 2981.61 1631.01 ;
END
END PORT_PAD[15]
PIN PORT_PAD[14]
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2980.11 1632.51 2981.61 1634.01 ;
END
END PORT_PAD[14]
PIN PORT_PAD[13]
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2980.11 1635.51 2981.61 1637.01 ;
END
END PORT_PAD[13]
PIN PORT_PAD[12]
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2980.11 1638.51 2981.61 1640.01 ;
END
END PORT_PAD[12]
PIN PORT_PAD[11]
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2980.11 1641.51 2981.61 1643.01 ;
END
END PORT_PAD[11]
PIN PORT_PAD[10]
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2980.11 1644.51 2981.61 1646.01 ;
END
END PORT_PAD[10]
PIN PORT_PAD[9]
USE SIGNAL ;
PORT
LAYER AT ;
RECT 2980.11 1647.51 2981.61 1649.01 ;
END
END PORT_PAD[9]
PIN SYN_FRAC_DIV[8]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2180.93 635.65 2181.43 ;
END
END SYN_FRAC_DIV[8]
PIN SYN_FRAC_DIV[7]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2181.93 635.65 2182.43 ;
END
END SYN_FRAC_DIV[7]
PIN SYN_FRAC_DIV[6]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2182.93 635.65 2183.43 ;
END
END SYN_FRAC_DIV[6]
PIN LDO_FIFO_EN
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2867.21 352.285 2867.71 352.785 ;
END
END LDO_FIFO_EN
PIN LDO_BM_EN
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2867.21 353.085 2867.71 353.585 ;
END
END LDO_BM_EN
PIN SYN_FRAC_DIV[5]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2183.93 635.65 2184.43 ;
END
END SYN_FRAC_DIV[5]
PIN SYN_FRAC_DIV[4]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2184.93 635.65 2185.43 ;
END
END SYN_FRAC_DIV[4]
PIN SYN_FRAC_DIV[3]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2185.93 635.65 2186.43 ;
END
END SYN_FRAC_DIV[3]
PIN SYN_FRAC_DIV[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2186.93 635.65 2187.43 ;
END
END SYN_FRAC_DIV[2]
PIN SYN_FRAC_DIV[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2187.93 635.65 2188.43 ;
END
END SYN_FRAC_DIV[1]
PIN SYN_FRAC_DIV[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2188.93 635.65 2189.43 ;
END
END SYN_FRAC_DIV[0]
PIN TX_QDAC_DI[5]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2301.115 635.65 2301.615 ;
END
END TX_QDAC_DI[5]
PIN TX_QDAC_DI[4]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2302.51 635.65 2303.01 ;
END
END TX_QDAC_DI[4]
PIN TX_QDAC_DI[3]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2303.74 635.65 2304.24 ;
END
END TX_QDAC_DI[3]
PIN PORT_OEN[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1633.41 2968.28 1633.91 ;
END
END PORT_OEN[1]
PIN PORT_OEN[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1634.41 2968.28 1634.91 ;
END
END PORT_OEN[0]
PIN PORT_C[18]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1636.985 2968.28 1637.485 ;
END
END PORT_C[18]
PIN PORT_C[17]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1637.985 2968.28 1638.485 ;
END
END PORT_C[17]
PIN PORT_C[16]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1638.985 2968.28 1639.485 ;
END
END PORT_C[16]
PIN PORT_C[15]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1639.985 2968.28 1640.485 ;
END
END PORT_C[15]
PIN PORT_C[14]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1640.985 2968.28 1641.485 ;
END
END PORT_C[14]
PIN PORT_C[13]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1641.985 2968.28 1642.485 ;
END
END PORT_C[13]
PIN PORT_C[12]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1642.985 2968.28 1643.485 ;
END
END PORT_C[12]
PIN PORT_C[11]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1643.985 2968.28 1644.485 ;
END
END PORT_C[11]
PIN PORT_C[10]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1644.985 2968.28 1645.485 ;
END
END PORT_C[10]
PIN PORT_C[9]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1645.985 2968.28 1646.485 ;
END
END PORT_C[9]
PIN PORT_C[8]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1646.985 2968.28 1647.485 ;
END
END PORT_C[8]
PIN PORT_C[7]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1647.985 2968.28 1648.485 ;
END
END PORT_C[7]
PIN PORT_C[6]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1648.985 2968.28 1649.485 ;
END
END PORT_C[6]
PIN PORT_C[5]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1649.985 2968.28 1650.485 ;
END
END PORT_C[5]
PIN PORT_C[4]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1650.985 2968.28 1651.485 ;
END
END PORT_C[4]
PIN PORT_C[3]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1651.985 2968.28 1652.485 ;
END
END PORT_C[3]
PIN PORT_C[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1652.985 2968.28 1653.485 ;
END
END PORT_C[2]
PIN PORT_C[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1653.985 2968.28 1654.485 ;
END
END PORT_C[1]
PIN PORT_C[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2967.78 1654.985 2968.28 1655.485 ;
END
END PORT_C[0]
PIN SAR_ADC_OUT[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1656.25 833.145 1656.75 ;
END
END SAR_ADC_OUT[0]
PIN SAR_ADC_OUT[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1658.41 833.145 1658.91 ;
END
END SAR_ADC_OUT[1]
PIN SAR_ADC_OUT[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1670.23 833.145 1670.73 ;
END
END SAR_ADC_OUT[2]
PIN SAR_ADC_OUT[3]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1672.39 833.145 1672.89 ;
END
END SAR_ADC_OUT[3]
PIN SAR_ADC_OUT[4]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1684.21 833.145 1684.71 ;
END
END SAR_ADC_OUT[4]
PIN SAR_ADC_OUT[5]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1686.37 833.145 1686.87 ;
END
END SAR_ADC_OUT[5]
PIN SAR_ADC_OUT[6]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1698.19 833.145 1698.69 ;
END
END SAR_ADC_OUT[6]
PIN SAR_ADC_OUT[7]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1700.35 833.145 1700.85 ;
END
END SAR_ADC_OUT[7]
PIN CE_C
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2883.755 1839.155 2884.255 1839.655 ;
END
END CE_C
PIN CSN_C
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2883.755 1924.155 2884.255 1924.655 ;
END
END CSN_C
PIN SCK_C
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2883.755 2009.155 2884.255 2009.655 ;
END
END SCK_C
PIN MOSI_C
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2883.755 2094.155 2884.255 2094.655 ;
END
END MOSI_C
PIN TX_EN_N_I
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2883.755 2303.71 2884.255 2304.21 ;
END
END TX_EN_N_I
PIN MISO_I
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2883.755 2218.71 2884.255 2219.21 ;
END
END MISO_I
PIN TRX_BG_PWD
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1599.265 833.145 1599.765 ;
END
END TRX_BG_PWD
PIN RX_ADC_TEST_OUT
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1597.925 833.145 1598.425 ;
END
END RX_ADC_TEST_OUT
PIN RX_ADC_TST[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1596.7 833.145 1597.2 ;
END
END RX_ADC_TST[0]
PIN RX_ADC_TST[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1595.32 833.145 1595.82 ;
END
END RX_ADC_TST[1]
PIN RX_REG_ADJ[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1589.56 833.145 1590.06 ;
END
END RX_REG_ADJ[0]
PIN RX_REG_ADJ[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1575.73 833.145 1576.23 ;
END
END RX_REG_ADJ[1]
PIN SYN_VCO_PWD
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1603.45 833.145 1603.95 ;
END
END SYN_VCO_PWD
PIN SYN_VCO_IS[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1571.34 833.145 1571.84 ;
END
END SYN_VCO_IS[0]
PIN SYN_VCO_IS[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1572.14 833.145 1572.64 ;
END
END SYN_VCO_IS[2]
PIN RX_PPF_PWD
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1522.925 833.145 1523.425 ;
END
END RX_PPF_PWD
PIN RX_BI_QUAD1_GAIN[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 232.495 833.145 232.995 ;
END
END RX_BI_QUAD1_GAIN[1]
PIN SAR_ADC_ENABLE
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1456.935 833.145 1457.435 ;
END
END SAR_ADC_ENABLE
PIN SAR_ADC_TEST_POINT[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1506.125 833.145 1506.625 ;
END
END SAR_ADC_TEST_POINT[1]
PIN RX_PPF_CAL_ENABLE
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1546.565 833.145 1547.065 ;
END
END RX_PPF_CAL_ENABLE
PIN RX_RSSI_ADC_CLK[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1513.325 833.145 1513.825 ;
END
END RX_RSSI_ADC_CLK[0]
PIN RX_RSSI_ADC_CLK[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1514.125 833.145 1514.625 ;
END
END RX_RSSI_ADC_CLK[1]
PIN RX_RSSI_VT[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1512.525 833.145 1513.025 ;
END
END RX_RSSI_VT[0]
PIN RX_RSSI_VT[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1511.725 833.145 1512.225 ;
END
END RX_RSSI_VT[1]
PIN RX_RSSI_VT[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1510.925 833.145 1511.425 ;
END
END RX_RSSI_VT[2]
PIN RX_RSSI_VT[3]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1510.125 833.145 1510.625 ;
END
END RX_RSSI_VT[3]
PIN RX_PPF_CAL_OUT[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1518.125 833.145 1518.625 ;
END
END RX_PPF_CAL_OUT[0]
PIN RX_PPF_CAL_OUT[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1517.325 833.145 1517.825 ;
END
END RX_PPF_CAL_OUT[1]
PIN RX_PPF_CAL_OUT[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1516.525 833.145 1517.025 ;
END
END RX_PPF_CAL_OUT[2]
PIN RX_PPF_CAL_OUT[3]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1515.725 833.145 1516.225 ;
END
END RX_PPF_CAL_OUT[3]
PIN RX_PPF_CAL_OUT[4]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1514.925 833.145 1515.425 ;
END
END RX_PPF_CAL_OUT[4]
PIN RX_ADC_BUF_IC
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1504.125 833.145 1504.625 ;
END
END RX_ADC_BUF_IC
PIN RX_BI_QUAD1_GAIN[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 233.295 833.145 233.795 ;
END
END RX_BI_QUAD1_GAIN[0]
PIN RX_PGA_PWD
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 242.095 833.145 242.595 ;
END
END RX_PGA_PWD
PIN SAR_ADC_TEST_POINT[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1482.815 833.145 1483.315 ;
END
END SAR_ADC_TEST_POINT[2]
PIN RX_ADC_OUT[7]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 343.345 833.145 343.845 ;
END
END RX_ADC_OUT[7]
PIN TRX_PWD
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 247.295 833.145 247.795 ;
END
END TRX_PWD
PIN RX_BI_QUAD2_GAIN[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1543.365 833.145 1543.865 ;
END
END RX_BI_QUAD2_GAIN[0]
PIN RX_BI_QUAD2_GAIN[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1542.565 833.145 1543.065 ;
END
END RX_BI_QUAD2_GAIN[1]
PIN RX_PPF_CAL_SEL
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 231.695 833.145 232.195 ;
END
END RX_PPF_CAL_SEL
PIN SYN_REF_DIV[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 230.895 833.145 231.395 ;
END
END SYN_REF_DIV[0]
PIN SYN_REF_DIV[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 230.095 833.145 230.595 ;
END
END SYN_REF_DIV[1]
PIN SYN_VCO_IS[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1570.54 833.145 1571.04 ;
END
END SYN_VCO_IS[1]
PIN RX_PGA_IS[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 238.095 833.145 238.595 ;
END
END RX_PGA_IS[0]
PIN RX_PGA_IS[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 237.295 833.145 237.795 ;
END
END RX_PGA_IS[1]
PIN RX_PGA_IS[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 236.495 833.145 236.995 ;
END
END RX_PGA_IS[2]
PIN RX_PGA_GAIN[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 240.495 833.145 240.995 ;
END
END RX_PGA_GAIN[0]
PIN RX_PGA_GAIN[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 239.695 833.145 240.195 ;
END
END RX_PGA_GAIN[1]
PIN RX_PGA_GAIN[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 238.895 833.145 239.395 ;
END
END RX_PGA_GAIN[2]
PIN RX_PPF_BW_SEL[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1541.765 833.145 1542.265 ;
END
END RX_PPF_BW_SEL[0]
PIN RX_PPF_BW_SEL[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1540.965 833.145 1541.465 ;
END
END RX_PPF_BW_SEL[1]
PIN RX_PPF_IS[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 235.695 833.145 236.195 ;
END
END RX_PPF_IS[0]
PIN RX_PPF_IS[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 234.895 833.145 235.395 ;
END
END RX_PPF_IS[1]
PIN RX_PPF_IS[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 234.095 833.145 234.595 ;
END
END RX_PPF_IS[2]
PIN RX_PPF_CAL_IN[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1522.125 833.145 1522.625 ;
END
END RX_PPF_CAL_IN[0]
PIN RX_PPF_CAL_IN[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1521.325 833.145 1521.825 ;
END
END RX_PPF_CAL_IN[1]
PIN RX_PPF_CAL_IN[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1520.525 833.145 1521.025 ;
END
END RX_PPF_CAL_IN[2]
PIN RX_PPF_CAL_IN[3]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1519.725 833.145 1520.225 ;
END
END RX_PPF_CAL_IN[3]
PIN RX_PPF_CAL_IN[4]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 1518.925 833.145 1519.425 ;
END
END RX_PPF_CAL_IN[4]
PIN XTAL_SU_IS[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2240.75 635.65 2241.25 ;
END
END XTAL_SU_IS[2]
PIN XTAL_SU_IS[3]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2240.07 635.65 2240.57 ;
END
END XTAL_SU_IS[3]
PIN clk_16m
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2266.655 635.65 2267.155 ;
END
END clk_16m
PIN RX_ADC_CLK_SEL
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2254.41 635.65 2254.91 ;
END
END RX_ADC_CLK_SEL
PIN XTAL_SU_EN
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2209.295 635.65 2209.795 ;
END
END XTAL_SU_EN
PIN PA_VDD_ADJ[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2207.695 635.65 2208.195 ;
END
END PA_VDD_ADJ[0]
PIN PA_VDD_ADJ[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2206.895 635.65 2207.395 ;
END
END PA_VDD_ADJ[1]
PIN TX_PA_GAIN[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2257.92 635.65 2258.42 ;
END
END TX_PA_GAIN[2]
PIN TX_PA_GAIN[3]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2260.32 635.65 2260.82 ;
END
END TX_PA_GAIN[3]
PIN TX_RF_MIXER_PWD
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2214.435 635.65 2214.935 ;
END
END TX_RF_MIXER_PWD
PIN TRX_MATCH_CT
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2239.39 635.65 2239.89 ;
END
END TRX_MATCH_CT
PIN XTAL_CAP[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2229.585 635.65 2230.085 ;
END
END XTAL_CAP[0]
PIN XTAL_CAP[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2228.905 635.65 2229.405 ;
END
END XTAL_CAP[1]
PIN XTAL_CAP[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2228.225 635.65 2228.725 ;
END
END XTAL_CAP[2]
PIN XTAL_CAP[3]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2227.545 635.65 2228.045 ;
END
END XTAL_CAP[3]
PIN TX_PA_GAIN[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2259.52 635.65 2260.02 ;
END
END TX_PA_GAIN[0]
PIN TX_PA_GAIN[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2258.72 635.65 2259.22 ;
END
END TX_PA_GAIN[1]
PIN SYN_EN_125K
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2210.095 635.65 2210.595 ;
END
END SYN_EN_125K
PIN XTAL_SB_IS[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2244.83 635.65 2245.33 ;
END
END XTAL_SB_IS[0]
PIN XTAL_SB_IS[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2245.51 635.65 2246.01 ;
END
END XTAL_SB_IS[1]
PIN XTAL_SB_IS[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2246.19 635.65 2246.69 ;
END
END XTAL_SB_IS[2]
PIN XTAL_SB_IS[3]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2246.87 635.65 2247.37 ;
END
END XTAL_SB_IS[3]
PIN RX_LNA_GAIN[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2215.235 635.65 2215.735 ;
END
END RX_LNA_GAIN[0]
PIN RX_LNA_GAIN[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2216.035 635.65 2216.535 ;
END
END RX_LNA_GAIN[1]
PIN RX_LNA_GAIN[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2211.235 635.65 2211.735 ;
END
END RX_LNA_GAIN[2]
PIN RX_LNA_TANK_CT[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2216.835 635.65 2217.335 ;
END
END RX_LNA_TANK_CT[0]
PIN RX_LNA_TANK_CT[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2217.635 635.65 2218.135 ;
END
END RX_LNA_TANK_CT[1]
PIN RX_LNA_TANK_CT[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2218.435 635.65 2218.935 ;
END
END RX_LNA_TANK_CT[2]
PIN SYN_EN_16M
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2867.21 268.69 2867.71 269.19 ;
END
PORT
LAYER A3 ;
RECT 635.15 2208.495 635.65 2208.995 ;
END
END SYN_EN_16M
PIN TX_PA_IS[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2221.635 635.65 2222.135 ;
END
END TX_PA_IS[0]
PIN TX_PA_IS[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2220.835 635.65 2221.335 ;
END
END TX_PA_IS[1]
PIN TX_PA_IS[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2220.035 635.65 2220.535 ;
END
END TX_PA_IS[2]
PIN TX_PA_IS[3]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2219.235 635.65 2219.735 ;
END
END TX_PA_IS[3]
PIN clk_125k
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2249.245 635.65 2249.745 ;
END
END clk_125k
PIN TX_RF_MIXER_TK[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2213.635 635.65 2214.135 ;
END
END TX_RF_MIXER_TK[0]
PIN TX_RF_MIXER_TK[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2212.835 635.65 2213.335 ;
END
END TX_RF_MIXER_TK[1]
PIN TX_RF_MIXER_TK[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2212.035 635.65 2212.535 ;
END
END TX_RF_MIXER_TK[2]
PIN TX_PA_PWD
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2222.435 635.65 2222.935 ;
END
END TX_PA_PWD
PIN XTAL_IS[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2244.15 635.65 2244.65 ;
END
END XTAL_IS[0]
PIN XTAL_IS[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2243.47 635.65 2243.97 ;
END
END XTAL_IS[1]
PIN XTAL_IS[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2242.79 635.65 2243.29 ;
END
END XTAL_IS[2]
PIN XTAL_SU_IS[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2242.11 635.65 2242.61 ;
END
END XTAL_SU_IS[0]
PIN XTAL_SU_IS[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2241.43 635.65 2241.93 ;
END
END XTAL_SU_IS[1]
PIN SYN_AFC_NEXT[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2037.055 635.65 2037.555 ;
END
END SYN_AFC_NEXT[0]
PIN SYN_AFC_NEXT[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2038.175 635.65 2038.675 ;
END
END SYN_AFC_NEXT[1]
PIN DIG_LDO_PWD
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 2867.21 267.375 2867.71 267.875 ;
END
END DIG_LDO_PWD
PIN DVDD_BM
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER A3 ;
RECT 2867.21 353.99 2867.71 363.89 ;
END
END DVDD_BM
PIN DVDD_FIFO
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER A3 ;
RECT 2867.21 364.25 2867.71 374.15 ;
END
END DVDD_FIFO
PIN SYN_FRAC_DIV[14]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2174.93 635.65 2175.43 ;
END
END SYN_FRAC_DIV[14]
PIN SYN_FRAC_DIV[13]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2175.93 635.65 2176.43 ;
END
END SYN_FRAC_DIV[13]
PIN SYN_FRAC_DIV[12]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2176.93 635.65 2177.43 ;
END
END SYN_FRAC_DIV[12]
PIN SYN_FRAC_DIV[11]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2177.93 635.65 2178.43 ;
END
END SYN_FRAC_DIV[11]
PIN SYN_FRAC_DIV[10]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2178.93 635.65 2179.43 ;
END
END SYN_FRAC_DIV[10]
PIN SYN_FRAC_DIV[9]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2179.93 635.65 2180.43 ;
END
END SYN_FRAC_DIV[9]
PIN IRQ1_N_I
USE SIGNAL ;
PORT
LAYER A2 ;
RECT 2791.63 2308.575 2792.13 2309.075 ;
END
END IRQ1_N_I
PIN TEST_MODE_C[0]
USE SIGNAL ;
PORT
LAYER A2 ;
RECT 2789.2 2308.575 2789.7 2309.075 ;
END
END TEST_MODE_C[0]
PIN TEST_MODE_C[1]
USE SIGNAL ;
PORT
LAYER A2 ;
RECT 2786.505 2308.575 2787.005 2309.075 ;
END
END TEST_MODE_C[1]
PIN spi_rst_n
USE SIGNAL ;
PORT
LAYER A2 ;
RECT 2933.275 1399.02 2933.775 1399.52 ;
END
END spi_rst_n
PIN fifo_rst_n
USE SIGNAL ;
PORT
LAYER A2 ;
RECT 2905.11 1399.02 2905.61 1399.52 ;
END
END fifo_rst_n
PIN RST_N_C
USE SIGNAL ;
PORT
LAYER A2 ;
RECT 2795.705 2308.575 2796.205 2309.075 ;
END
END RST_N_C
PIN bm_rst_n
USE SIGNAL ;
PORT
LAYER A2 ;
RECT 2899.86 1399.02 2900.36 1399.52 ;
END
END bm_rst_n
PIN CLK_16M_I
USE SIGNAL ;
PORT
LAYER A2 ;
RECT 2804.48 2308.575 2804.98 2309.075 ;
END
END CLK_16M_I
PIN TX_EN_I
USE SIGNAL ;
PORT
LAYER A2 ;
RECT 2826.57 2308.575 2827.07 2309.075 ;
END
END TX_EN_I
PIN IRQ0_N_I
USE SIGNAL ;
PORT
LAYER A2 ;
RECT 2793.83 2308.575 2794.33 2309.075 ;
END
END IRQ0_N_I
PIN TX_QDAC_DI[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2305.03 635.65 2305.53 ;
END
END TX_QDAC_DI[2]
PIN TX_QDAC_DI[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2306.44 635.65 2306.94 ;
END
END TX_QDAC_DI[1]
PIN TX_QDAC_DI[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2307.87 635.65 2308.37 ;
END
END TX_QDAC_DI[0]
PIN TX_IDAC_DI[6]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2291.585 635.65 2292.085 ;
END
END TX_IDAC_DI[6]
PIN TX_IDAC_DI[5]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2285.92 635.65 2286.42 ;
END
END TX_IDAC_DI[5]
PIN TX_IDAC_DI[4]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2284.505 635.65 2285.005 ;
END
END TX_IDAC_DI[4]
PIN TX_IDAC_DI[3]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2283.045 635.65 2283.545 ;
END
END TX_IDAC_DI[3]
PIN TX_IDAC_DI[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2281.625 635.65 2282.125 ;
END
END TX_IDAC_DI[2]
PIN TX_IDAC_DI[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2280.17 635.65 2280.67 ;
END
END TX_IDAC_DI[1]
PIN TX_IDAC_DI[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2278.735 635.65 2279.235 ;
END
END TX_IDAC_DI[0]
PIN SYN_PFD_PWD
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2191.935 635.65 2192.435 ;
END
END SYN_PFD_PWD
PIN SYN_DIV_PWD
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 1986.28 635.65 1986.78 ;
END
END SYN_DIV_PWD
PIN TX_DAC_CLK_SEL
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2293.335 635.65 2293.835 ;
END
END TX_DAC_CLK_SEL
PIN TX_PWD
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2310.065 635.65 2310.565 ;
END
END TX_PWD
PIN TX_DAC_IS[3]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2298.09 635.65 2298.59 ;
END
END TX_DAC_IS[3]
PIN TX_DAC_IS[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2297.09 635.65 2297.59 ;
END
END TX_DAC_IS[2]
PIN TX_DAC_IS[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2296.09 635.65 2296.59 ;
END
END TX_DAC_IS[1]
PIN TX_DAC_IS[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2295.09 635.65 2295.59 ;
END
END TX_DAC_IS[0]
PIN TX_QDAC_DI[6]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2299.59 635.65 2300.09 ;
END
END TX_QDAC_DI[6]
PIN SYN_CP_REG[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 1978.515 635.65 1979.015 ;
END
END SYN_CP_REG[1]
PIN SYN_CP_REG[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 1979.315 635.65 1979.815 ;
END
END SYN_CP_REG[0]
PIN TX_DAC_CM[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2290.145 635.65 2290.645 ;
END
END TX_DAC_CM[1]
PIN TX_DAC_CM[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2288.965 635.65 2289.465 ;
END
END TX_DAC_CM[0]
PIN TRX_BG_RES_SEL
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 1987.08 635.65 1987.58 ;
END
END TRX_BG_RES_SEL
PIN TX_IF_MIXER_PWD
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2309.065 635.65 2309.565 ;
END
END TX_IF_MIXER_PWD
PIN TX_IQ_DAC_PWD
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2287.45 635.65 2287.95 ;
END
END TX_IQ_DAC_PWD
PIN SYN_INT_DIV[6]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2312.1 635.65 2312.6 ;
END
END SYN_INT_DIV[6]
PIN SYN_INT_DIV[5]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2313.1 635.65 2313.6 ;
END
END SYN_INT_DIV[5]
PIN SYN_INT_DIV[4]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2314.1 635.65 2314.6 ;
END
END SYN_INT_DIV[4]
PIN SYN_INT_DIV[3]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2315.1 635.65 2315.6 ;
END
END SYN_INT_DIV[3]
PIN SYN_INT_DIV[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2316.1 635.65 2316.6 ;
END
END SYN_INT_DIV[2]
PIN SYN_INT_DIV[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2317.1 635.65 2317.6 ;
END
END SYN_INT_DIV[1]
PIN SYN_INT_DIV[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2318.1 635.65 2318.6 ;
END
END SYN_INT_DIV[0]
PIN SYN_AFC_C_AUTO[3]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 1982.28 635.65 1982.78 ;
END
END SYN_AFC_C_AUTO[3]
PIN SYN_AFC_C_AUTO[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 1983.08 635.65 1983.58 ;
END
END SYN_AFC_C_AUTO[2]
PIN SYN_AFC_C_AUTO[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 1983.88 635.65 1984.38 ;
END
END SYN_AFC_C_AUTO[1]
PIN SYN_AFC_C_AUTO[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 1984.68 635.65 1985.18 ;
END
END SYN_AFC_C_AUTO[0]
PIN SYN_CP_IS[3]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2103.015 635.65 2103.515 ;
END
END SYN_CP_IS[3]
PIN SYN_CP_IS[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2103.815 635.65 2104.315 ;
END
END SYN_CP_IS[2]
PIN SYN_CP_IS[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2104.615 635.65 2105.115 ;
END
END SYN_CP_IS[1]
PIN SYN_CP_IS[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2105.415 635.65 2105.915 ;
END
END SYN_CP_IS[0]
PIN SYN_AFC_MNL
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2024.735 635.65 2025.235 ;
END
END SYN_AFC_MNL
PIN SYN_PWD
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 1985.48 635.65 1985.98 ;
END
END SYN_PWD
PIN SYN_AFC_C_MNL[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2025.855 635.65 2026.355 ;
END
END SYN_AFC_C_MNL[0]
PIN SYN_AFC_C_MNL[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2026.975 635.65 2027.475 ;
END
END SYN_AFC_C_MNL[1]
PIN SYN_AFC_C_MNL[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2028.095 635.65 2028.595 ;
END
END SYN_AFC_C_MNL[2]
PIN SYN_AFC_C_MNL[3]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2029.215 635.65 2029.715 ;
END
END SYN_AFC_C_MNL[3]
PIN SYN_AFC_D[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2030.335 635.65 2030.835 ;
END
END SYN_AFC_D[0]
PIN SYN_AFC_D[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2031.455 635.65 2031.955 ;
END
END SYN_AFC_D[1]
PIN SYN_AFC_D[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2032.575 635.65 2033.075 ;
END
END SYN_AFC_D[2]
PIN SYN_AFC_D[3]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2033.695 635.65 2034.195 ;
END
END SYN_AFC_D[3]
PIN SYN_AFC_INI[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2034.815 635.65 2035.315 ;
END
END SYN_AFC_INI[0]
PIN SYN_AFC_INI[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2035.935 635.65 2036.435 ;
END
END SYN_AFC_INI[1]
PIN SYN_AFC_ADJ[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2039.295 635.65 2039.795 ;
END
END SYN_AFC_ADJ[0]
PIN SYN_AFC_ADJ[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2040.415 635.65 2040.915 ;
END
END SYN_AFC_ADJ[1]
PIN SYN_AFC_ADJ[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2041.535 635.65 2042.035 ;
END
END SYN_AFC_ADJ[2]
PIN SYN_FRAC_DIV[15]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2173.93 635.65 2174.43 ;
END
END SYN_FRAC_DIV[15]
PIN SYN_FRAC_DIV[16]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2172.93 635.65 2173.43 ;
END
END SYN_FRAC_DIV[16]
PIN SYN_FRAC_DIV[17]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2171.93 635.65 2172.43 ;
END
END SYN_FRAC_DIV[17]
PIN SYN_FRAC_DIV[18]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2170.93 635.65 2171.43 ;
END
END SYN_FRAC_DIV[18]
PIN SYN_FRAC_DIV[19]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2169.93 635.65 2170.43 ;
END
END SYN_FRAC_DIV[19]
PIN SYN_PFD_SEL
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2191.135 635.65 2191.635 ;
END
END SYN_PFD_SEL
PIN TX_LPF_SEL[2]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2273.655 635.65 2274.155 ;
END
END TX_LPF_SEL[2]
PIN TX_LPF_SEL[3]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2272.655 635.65 2273.155 ;
END
END TX_LPF_SEL[3]
PIN TX_LPF_SEL[0]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2275.655 635.65 2276.155 ;
END
END TX_LPF_SEL[0]
PIN TX_LPF_SEL[1]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 635.15 2274.655 635.65 2275.155 ;
END
END TX_LPF_SEL[1]
PIN DVDD_SPI
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER A3 ;
RECT 2867.21 414.85 2867.71 424.85 ;
END
END DVDD_SPI
PIN RX_ADC_OUT[6]
USE SIGNAL ;
PORT
LAYER A3 ;
RECT 832.645 342.345 833.145 342.845 ;
END
END RX_ADC_OUT[6]
OBS
LAYER A3 ;
RECT 0 2025.575 634.87 2026.635 ;
RECT 0 2025.515 635.65 2025.575 ;
RECT 0 2024.455 634.87 2025.515 ;
RECT 0 2023.845 635.65 2024.455 ;
RECT 0 2022.785 634.87 2023.845 ;
RECT 2883.755 2009.935 3002.95 2093.875 ;
RECT 2884.535 2008.875 3002.95 2009.935 ;
RECT 0 1987.86 635.65 2022.785 ;
RECT 0 1982 634.87 1987.86 ;
RECT 0 1980.095 635.65 1982 ;
RECT 0 1978.235 634.87 1980.095 ;
RECT 2883.755 1924.935 3002.95 2008.875 ;
RECT 2884.535 1923.875 3002.95 1924.935 ;
RECT 2883.755 1839.935 3002.95 1923.875 ;
RECT 2884.535 1838.875 3002.95 1839.935 ;
RECT 0 1822.86 635.65 1978.235 ;
RECT 0 1701.13 833.145 1822.86 ;
RECT 0 1700.07 832.365 1701.13 ;
RECT 0 1698.97 833.145 1700.07 ;
RECT 0 1697.91 832.365 1698.97 ;
RECT 2883.755 1692.195 3002.95 1838.875 ;
RECT 0 1687.15 833.145 1697.91 ;
RECT 0 1686.09 832.365 1687.15 ;
RECT 0 1684.99 833.145 1686.09 ;
RECT 0 1683.93 832.365 1684.99 ;
RECT 2967.78 1676.095 3002.95 1692.195 ;
RECT 0 1673.17 833.145 1683.93 ;
RECT 0 1672.11 832.365 1673.17 ;
RECT 0 1671.01 833.145 1672.11 ;
RECT 0 1669.95 832.365 1671.01 ;
RECT 0 1659.19 833.145 1669.95 ;
RECT 0 1658.13 832.365 1659.19 ;
RECT 2968.56 1657.035 3002.95 1676.095 ;
RECT 0 1657.03 833.145 1658.13 ;
RECT 0 1655.97 832.365 1657.03 ;
RECT 2967.78 1655.765 3002.95 1657.035 ;
RECT 2968.56 1636.705 3002.95 1655.765 ;
RECT 2967.78 1635.19 3002.95 1636.705 ;
RECT 2968.56 1616.13 3002.95 1635.19 ;
RECT 0 1604.23 833.145 1655.97 ;
RECT 0 1603.17 832.365 1604.23 ;
RECT 0 1600.045 833.145 1603.17 ;
RECT 0 1598.985 832.365 1600.045 ;
RECT 0 1598.705 833.145 1598.985 ;
RECT 0 1597.645 832.365 1598.705 ;
RECT 0 1597.48 833.145 1597.645 ;
RECT 0 1596.42 832.365 1597.48 ;
RECT 0 1596.1 833.145 1596.42 ;
RECT 0 1595.04 832.365 1596.1 ;
RECT 0 1590.34 833.145 1595.04 ;
RECT 0 1589.28 832.365 1590.34 ;
RECT 0 1576.51 833.145 1589.28 ;
RECT 0 1575.45 832.365 1576.51 ;
RECT 0 1572.92 833.145 1575.45 ;
RECT 0 1569.46 832.365 1572.92 ;
RECT 0 1565.28 833.145 1569.46 ;
RECT 0 1563.42 832.365 1565.28 ;
RECT 0 1552.145 833.145 1563.42 ;
RECT 0 1540.685 832.365 1552.145 ;
RECT 0 1523.705 833.145 1540.685 ;
RECT 0 1508.245 832.365 1523.705 ;
RECT 0 1506.905 833.145 1508.245 ;
RECT 0 1505.845 832.365 1506.905 ;
RECT 0 1504.905 833.145 1505.845 ;
RECT 0 1503.845 832.365 1504.905 ;
RECT 0 1494.205 833.145 1503.845 ;
RECT 0 1493.145 832.365 1494.205 ;
RECT 0 1483.595 833.145 1493.145 ;
RECT 0 1482.535 832.365 1483.595 ;
RECT 0 1472.985 833.145 1482.535 ;
RECT 0 1471.925 832.365 1472.985 ;
RECT 0 1457.715 833.145 1471.925 ;
RECT 0 1456.655 832.365 1457.715 ;
RECT 2967.78 1399.52 3002.95 1616.13 ;
RECT 0 512.795 833.145 1456.655 ;
RECT 0 511.735 832.365 512.795 ;
RECT 2867.21 425.45 3002.95 1399.52 ;
RECT 2868.31 414.25 3002.95 425.45 ;
RECT 2867.21 374.43 3002.95 414.25 ;
RECT 2867.99 352.005 3002.95 374.43 ;
RECT 0 344.125 833.145 511.735 ;
RECT 0 334.065 832.365 344.125 ;
RECT 2867.21 269.47 3002.95 352.005 ;
RECT 2867.99 268.41 3002.95 269.47 ;
RECT 2867.21 268.155 3002.95 268.41 ;
RECT 2867.99 267.095 3002.95 268.155 ;
RECT 0 248.075 833.145 334.065 ;
RECT 0 247.015 832.365 248.075 ;
RECT 0 245.275 833.145 247.015 ;
RECT 2867.21 150 3002.95 267.095 ;
RECT 0 229.815 832.365 245.275 ;
RECT 0 199.14 833.145 229.815 ;
RECT 0 150 865.27 199.14 ;
RECT 0 0 3002.95 150 ;
RECT 0 2391.66 702.51 2427.83 ;
RECT 0 2318.88 635.65 2391.66 ;
RECT 0 2311.82 634.87 2318.88 ;
RECT 0 2310.845 635.65 2311.82 ;
RECT 0 2308.785 634.87 2310.845 ;
RECT 0 2308.65 635.65 2308.785 ;
RECT 2694.315 2308.575 3002.95 2427.83 ;
RECT 0 2307.59 634.87 2308.65 ;
RECT 0 2307.22 635.65 2307.59 ;
RECT 0 2306.16 634.87 2307.22 ;
RECT 0 2305.81 635.65 2306.16 ;
RECT 0 2304.75 634.87 2305.81 ;
RECT 0 2304.52 635.65 2304.75 ;
RECT 2883.755 2304.49 3002.95 2308.575 ;
RECT 0 2303.46 634.87 2304.52 ;
RECT 2884.535 2303.43 3002.95 2304.49 ;
RECT 0 2303.29 635.65 2303.46 ;
RECT 0 2302.23 634.87 2303.29 ;
RECT 0 2301.895 635.65 2302.23 ;
RECT 0 2300.835 634.87 2301.895 ;
RECT 0 2300.37 635.65 2300.835 ;
RECT 0 2299.31 634.87 2300.37 ;
RECT 0 2298.87 635.65 2299.31 ;
RECT 0 2294.81 634.87 2298.87 ;
RECT 0 2294.115 635.65 2294.81 ;
RECT 0 2293.055 634.87 2294.115 ;
RECT 0 2292.365 635.65 2293.055 ;
RECT 0 2291.305 634.87 2292.365 ;
RECT 0 2290.925 635.65 2291.305 ;
RECT 0 2289.865 634.87 2290.925 ;
RECT 0 2289.745 635.65 2289.865 ;
RECT 0 2288.685 634.87 2289.745 ;
RECT 0 2288.23 635.65 2288.685 ;
RECT 0 2287.17 634.87 2288.23 ;
RECT 0 2286.7 635.65 2287.17 ;
RECT 0 2285.64 634.87 2286.7 ;
RECT 0 2285.285 635.65 2285.64 ;
RECT 0 2284.225 634.87 2285.285 ;
RECT 0 2283.825 635.65 2284.225 ;
RECT 0 2282.765 634.87 2283.825 ;
RECT 0 2282.405 635.65 2282.765 ;
RECT 0 2281.345 634.87 2282.405 ;
RECT 0 2280.95 635.65 2281.345 ;
RECT 0 2279.89 634.87 2280.95 ;
RECT 0 2279.515 635.65 2279.89 ;
RECT 0 2278.455 634.87 2279.515 ;
RECT 0 2276.435 635.65 2278.455 ;
RECT 0 2272.375 634.87 2276.435 ;
RECT 0 2267.435 635.65 2272.375 ;
RECT 0 2266.375 634.87 2267.435 ;
RECT 0 2261.1 635.65 2266.375 ;
RECT 0 2257.64 634.87 2261.1 ;
RECT 0 2255.19 635.65 2257.64 ;
RECT 0 2254.13 634.87 2255.19 ;
RECT 0 2250.025 635.65 2254.13 ;
RECT 0 2248.965 634.87 2250.025 ;
RECT 0 2247.65 635.65 2248.965 ;
RECT 0 2239.11 634.87 2247.65 ;
RECT 0 2230.365 635.65 2239.11 ;
RECT 0 2227.265 634.87 2230.365 ;
RECT 0 2223.215 635.65 2227.265 ;
RECT 2883.755 2219.49 3002.95 2303.43 ;
RECT 2884.535 2218.43 3002.95 2219.49 ;
RECT 0 2210.955 634.87 2223.215 ;
RECT 0 2210.875 635.65 2210.955 ;
RECT 0 2206.615 634.87 2210.875 ;
RECT 0 2192.715 635.65 2206.615 ;
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END
END ANA_TOP
END LIBRARY

复制代码

zg8312 · 发表于 2013-9-6 16:33:17

ls是我lef代码，不知道有没有什么问题！我使用这个lef还是会有上面的问题！

zzvbk · 发表于 2013-9-17 21:33:02

回复 1# zg8312

ASTRO 打开block的framview，用layer192层随便画个框框，保存退出即可！

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[求助] 为什么我的stdcell在macro外面place呢？

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