Phaselock Techniques(3rd) by Floyd M. Gardner

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Phaselock Techniques
Publication Date: July 29, 2005  | ISBN-10: 0471430633   | ISBN-13: 978-0471430636  | Edition: 3
Author:Floyd M. Gardner

Author:
1 INTRODUCTION 1
1.1 Salient Properties of PLLs  /  2
1.1.1 Bandwidth  /  2
1.1.2 Linearity  /  3
1.2 Organization of the Book  /  3
1.3 Annotated Bibliography  /  3
2 TRANSFER FUNCTIONS OF ANALOG PLLs 6
2.1 Basic Transfer Functions  /  6
2.1.1 Transfer Functions of Individual Elements  /  7
2.1.2 Combined Transfer Functions  /  8
2.1.3 Characteristic Equation  /  9
2.1.4 Nomenclature, Coefﬁcients, and Units  /  9
2.2 Second-Order PLLs  /  10
2.2.1 Loop Filters  /  10
2.2.2 Order and Type  /  12
viiviii CONTENTS
2.2.3 Loop Parameters  /  12
2.2.4 Frequency Response  /  15
2.3 Other Loop Types and Orders  /  20
2.3.1 General Deﬁnition of Loop Gain K /  20
2.3.2 Examples of Type 1 PLLs  /  22
2.3.3 Examples of Type 2 PLLs  /  24
2.3.4 Higher-Type PLLs  /  28
Reference /  28
3 GRAPHICAL AIDS 29
3.1 Root-Locus Plots  /  30
3.1.1 Description of Root-Locus Plots  /  30
3.1.2 Stability Criterion  /  33
3.1.3 Root Loci of Type 1 PLLs  /  33
3.1.4 Root Loci of Type 2 PLLs  /  33
3.1.5 Root Loci of Type 3 PLLs  /  34
3.1.6 Root Loci of Higher-Order PLLs  /  35
3.1.7 Effect of Loop Delay on Root Locus  /  38
3.2 Bode Plots  /  38
3.2.1 Presentation Options  /  38
3.2.2 Stability  /  39
3.2.3 Bode Plots of Type 1 PLLs  /  40
3.2.4 Bode Plots of Type 2 PLLs  /  43
3.2.5 Bode Plots of Type 3 PLLs  /  48
3.3 Nyquist Diagrams  /  49
3.4 Nichols Charts  /  49
3.4.1 Stability Criterion  /  49
3.4.2 M-Contours  /  50
3.4.3 Examples of Nichols Charts  /  50
3.5 Closed-Loop Frequency-Response Curves  /  52
Appendix 3A: Salient Features of Root Loci  /  52
3A.1 Branches of Root Loci  /  53
3A.2 Locus on the Real Axis  /  53
3A.3 Locus Intersections with Axes  /  54
Appendix 3B: Formats of the Open-Loop Transfer Function
G(s) /  56
3B.1 Proportional-Plus-Integral Section  /  56
3B.2 High-Frequency Section  /  60
3B.3 Calculations  /  60CONTENTS ix
Appendix 3C: Closed-Loop Frequency Responses  /  61
3C.1 Frequency-Response Formulas  /  61
3C.2 Example Frequency-Response Graphs  /  61
References /  64
4 DIGITAL PLLs: TRANSFER FUNCTIONS AND
RELATED TOOLS 65
4.1 Distinctive Properties of Digital PLLs  /  65
4.2 Digital Transfer Function  /  66
4.2.1 Conﬁguration of a Digital PLL  /  66
4.2.2 Difference Equations  /  67
4.2.3 z-Transforms of the Loop Elements  /  69
4.2.4 Loop Filter  /  70
4.2.5 Loop Transfer Functions  /  71
4.2.6 Poles and Zeros  /  71
4.3 Loop Stability  /  73
4.3.1 Type 1 DPLLs  /  73
4.3.2 Type 2 DPLLs  /  73
4.3.3 Type 3 DPLLs  /  74
4.4 Root-Locus Plots  /  74
4.4.1 Root Loci of Type 1 DPLLs  /  75
4.4.2 Root Loci of Type 2 DPLLs  /  75
4.4.3 Root Loci of Type 3 DPLLs  /  78
4.5 DPLL Frequency Responses: Formulation  /  79
4.6 Bode Plots and Nichols Charts  /  80
4.6.1 Basis of Bode Plots  /  80
4.6.2 Bode Stability Criteria  /  81
4.6.3 Bode Plots of Example DPLLs  /  81
4.6.4 Nichols Chart Example  /  83
4.7 Time-Continuous Approximation for a DPLL  /  85
4.8 Frequency-Response Examples  /  86
4.8.1 Effect of Delay  /  86
4.8.2 Effect of Bandwidth  /  87
4.9 Lowpass Filters in the Loop  /  88
4.9.1 Inﬁnite Impulse Response Lowpass Filter  /  88
4.9.2 Finite Impulse Response Lowpass Filter  /  90
Appendix 4A: Stability of Digital Phaselock Loops  /  91
4A.1 Type 1 DPLL  /  92
4A.2 Type 2 DPLL  /  93
Reference /  96x CONTENTS
5 TRACKING 97
5.1 Linear Tracking  /  97
5.1.1 Steady-State Phase Errors  /  98
5.1.2 Transient Response  /  100
5.1.3 Response to Sinusoidal Angle Modulation  /  109
5.2 Nonlinear Tracking: Lock Limits  /  112
5.2.1 Phase-Detector Nonlinearity  /  112
5.2.2 Steady-State Limits  /  112
5.2.3 Transient Limits  /  114
5.2.4 Modulation Limits  /  118
References /  121
6 EFFECTS OF ADDITIVE NOISE 123
6.1 Linear Operation  /  123
6.1.1 Noise Model of a Phase Detector  /  123
6.1.2 Noise Transfer Function  /  129
6.1.3 Noise Bandwidth  /  129
6.1.4 Signal-to-Noise Ratio in a PLL  /  131
6.1.5 Optimality  /  132
6.2 Nonlinear Operation  /  132
6.2.1 Observed Behavior  /  133
6.2.2 Nonlinear Analysis of Phase Error  /  135
6.2.3 Probability Density and Variance  /  136
6.2.4 Cycle Slips  /  137
6.2.5 Experimental and Simulation Results  /  138
6.2.6 Approximate Analyses  /  138
6.2.7 Miscellaneous Features  /  139
References /  141
7 EFFECTS OF PHASE NOISE 143
7.1 Properties of Phase Noise  /  144
7.1.1 Oscillator Model  /  144
7.1.2 Neglect of Amplitude Noise  /  144
7.1.3 Variance  /  144
7.1.4 Nonstationarity  /  144
7.2 Spectra of Phase Noise  /  146
7.2.1 Theoretical Spectrum W vo (f ) /  146
7.2.2 Normalized Spectrum L (f ) /  147
7.2.3 RF Spectra WRF(f ) and PRF(f ) /  147
7.2.4 Phase-Noise Spectrum W φ (f ) /  149CONTENTS xi
7.2.5 Frequency-Noise Spectrum W ω (f ) /  152
7.2.6 Example Phase-Noise Spectrum  /  152
7.3 Properties of Phase-Noise Spectra  /  153
7.3.1 Typical Continuous Spectra  /  154
7.3.2 Meaning of W φ (f ) /  155
7.3.3 Interpretation of Spectral Displays  /  156
7.3.4 Relationship Between W φ (f ) and L (f ) /  157
7.4 Propagation of Phase Noise  /  159
7.4.1 Phase-Noise Propagation in Auxiliary
Devices  /  159
7.4.2 Phase-Noise Propagation in PLLs  /  161
7.5 Integrated Phase Noise in PLLs  /  162
7.5.1 Basic Formulas  /  162
7.5.2 Excessive Phase Noise  /  163
7.5.3 Effect on Coherent Demodulation  /  163
7.5.4 Bandwidth Trade-off  /  163
7.5.5 Integration  /  164
7.5.6 A Paradox  /  165
7.5.7 Integration of Spectral Lines  /  166
7.5.8 Phase-Noise Speciﬁcations  /  166
7.6 Timing Jitter  /  167
Appendix 7A: Analysis of Interference in a Hard
Limiter  /  168
Appendix 7B: Integrals of Untracked Phase Noise  /  169
7B.1 Integration Procedures /  169
7B.2 Results of Integrations  /  169
7B.3 Discussion  /  171
Appendix 7C: Numerical Integration of PLL Phase
Noise  /  171
7C.1 Deﬁnition and Application of Integrated Phase
Noise  /  172
7C.2 Data Formats  /  172
7C.3 Data Adjustments  /  173
7C.4 Data Filtering  /  174
7C.5 Numerical Integration  /  174
Appendix 7D: Integration of Discrete Lines in the
Phase-Noise Spectrum  /  175
Appendix 7E: Timing Jitter  /  177
7E.1 Jitter Deﬁnitions  /  177
7E.2 Jitter in PLLs  /  179
References /  180xii CONTENTS
8 ACQUISITION OF PHASELOCK 183
8.1 Characterization  /  183
8.2 Phase Acquisition  /  184
8.2.1 First-Order Loop  /  184
8.2.2 Hang-up  /  186
8.2.3 Lock-in  /  186
8.2.4 Aided Phase Acquisition  /  188
8.3 Frequency Acquisition  /  189
8.3.1 Frequency Pull-in  /  189
8.3.2 Frequency Sweeping  /  195
8.3.3 Discriminator-Aided Frequency Acquisition  /  199
8.3.4 Implementation of Frequency
Discriminators  /  203
8.4 Diverse Matters  /  204
8.4.1 Lock Indicators  /  204
8.4.2 Wide-Bandwidth Methods  /  205
8.4.3 Memory  /  206
References /  206
9 OSCILLATORS 209
9.1 Desired Properties  /  209
9.2 Classes of Oscillators  /  210
9.3 Phase Noise in Oscillators: Simpliﬁed Approach  /  210
9.3.1 Leeson’s Model  /  210
9.3.2 Guides for Oscillator Design  /  212
9.3.3 Example Phase-Noise Spectra  /  213
9.3.4 Shortcomings of Leeson’s Model  /  214
9.4 Classiﬁcations of Oscillators  /  215
9.5 Phase Noise in Oscillators: Advanced Analysis  /  217
9.5.1 Impulse Sensitivity Function  /  218
9.5.2 Nonlinear Analyses for Phase Noise  /  219
9.6 Other Disturbances  /  221
9.7 Types of Oscillator Tuning  /  223
9.7.1 Continuous-Tuning Oscillators  /  223
9.7.2 Discrete-Tuning Oscillators  /  224
9.8 Tuning of Analog VCOs  /  226
9.8.1 Tuning Curve  /  227
9.8.2 Tuning Methods  /  228
9.8.3 Speed of Tuning  /  231
References /  232CONTENTS xiii
10 PHASE DETECTORS 237
10.3.6 Effects of Delay in a PFD  /  254
10.3.7 Extra or Missed Transitions  /  255
10.3.8 Lock Indicator for a PFD  /  256
Appendix 10A: Phase Modulation Due to Phase-Detector
Ripple  /  262
10A.1 Ripple Model  /  262
10A.2 Basis of Analysis  /  263
10A.3 Ripple Examples  /  263
10A.4 Ripple Filters  /  264
References /  265
11 LOOP FILTERS 267
11.1 Active vs. Passive Loop Filters  /  267
11.2 DC Offset  /  268
11.3 Transient Overload  /  269
11.3.1 Overload from PD Ripple  /  269
11.3.2 Overload During Acquisition  /  269
12 CHARGE-PUMP PHASELOCK LOOPS 271
12.1 Model of a Charge Pump  /  271
12.7 Late Developments  /  280
References /  281
13 DIGITAL (SAMPLED) PHASELOCK LOOPS 282
13.1 QuasiLinear Sampled PLLs  /  283
13.2.1 Lessons from Related Studies  /  294

DPLL  /  327
13A.1 Nomenclature  /  327
13A.2 Phase-Detector Operation  /  327
13A.6 Transfer Functions  /  330
13A.7 Transfer Function of a Hold Filter  /  332
References /  333CONTENTS xv
14 ANOMALOUS LOCKING 336
14.1 Sidelocks  /  336
14.1.1 Periodic Modulations  /  337
14.1.2 Cyclostationary Modulations  /  338
14.5 Lock Failures in Chains of PLLs  /  353
References /  354
15 PLL FREQUENCY SYNTHESIZERS 357
15.1 Synthesizer Conﬁgurations  /  357
15.1.1 Basic Conﬁguration  /  357
15.1.2 Alternative Conﬁgurations  /  359
15.2 Frequency Dividers  /  360
15.2.1 Analog Frequency Dividers  /  361
15.2.2 Digital Counters as Frequency Dividers  /  361
15.3 Fractional-N Counters  /  362
15.3.1 Dual-Modulus Counters  /  362
15.3.2 Fractional-N PLLs with Analog
Compensation  /  364
15.3.3 Fractional-N PLLs with Delta–Sigma
16 PHASELOCK MODULATORS AND DEMODULATORS 380

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