synplify ready ip core and other

speak48 · 发表于 2013-3-19 03:57:26

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本帖最后由 speak48 于 2013-4-14 02:47 编辑

examples encryted ip i find that on net
http://read.pudn.com/downloads152/sourcecode/embed/668240/CAST_jpeg_d-xact/JPEG_D/openip/hdl/verilog/jpeg_d/jpeg_d_core.v__.htm
see attach whats inside

so send me encrypted any 3rd party ip for decryption

`include "jpeg_d_package.v"
module jpeg_d_core (clk, hd_clk_en, en, rst, clr, mp_out_common_cbus, mp_out_d_cbus, mp_in_d_cbus, pixout_rdy, pixout, pixout_wen, pixout_eob, pixout_lbs, pixout_sob, scanactive, soi_eoi, eos, streamdin, streamfifodatavalid, streamren, ps_fifo_in_cbus, ps_fifo_out_cbus, dht_raddr, dht_dout, idct_in_cbus, idct_out_cbus, idctbuffer_dout, idctbuffer_out_cbus, qt_dout, qtables_out_cbus);
input clk; // Global clock
input hd_clk_en; // Global clock enable
input en; // Enable
input rst; // Asynchronous reset
input clr; // Synchronous clear
input[82:0] mp_out_common_cbus; // Data/control bus from markers' parser (common to encode and decode)
input[42:0] mp_out_d_cbus; // Data/control bus from markers' parser (only for decoder)
output[3:0] mp_in_d_cbus; // Data/control bus to markers' parser from decoder
wire[3:0] mp_in_d_cbus;
input pixout_rdy; // Ready to accept pixel data
output[7:0] pixout; // Pixel out data
wire[7:0] pixout;
output pixout_wen; // Pixel out data write enable
wire pixout_wen;
output pixout_eob; // End of block flag. Masks last sample of each block
wire pixout_eob;
output pixout_lbs; // Last block in scan flag. Masks last block's samples
wire pixout_lbs;
output pixout_sob; // Start of block flag. Masks first sample of each block.
wire pixout_sob;
output scanactive; // Scan-active flag (asserted when the decoder processes ecs data)
wire scanactive;
output[1:0] soi_eoi; // SOI-EOI flags. Asserted when the corresponding marker has been detected.
wire[1:0] soi_eoi;
output eos; // End Of Scan indicator
wire eos;
input[7:0] streamdin; // Data from stream fifo
input streamfifodatavalid; // Data valid flag for data coming from stream fifo
output streamren; // Stream fifo read enable
wire streamren;
input[33:0] ps_fifo_in_cbus; // Control/data bus from Huffman decoder's ouptut fifo
output[35:0] ps_fifo_out_cbus; // Control/data bus to Huffman decoder's ouptut fifo
wire[35:0] ps_fifo_out_cbus;
output[8:0] dht_raddr; // Huffman tables read address
wire[8:0] dht_raddr;
input[7:0] dht_dout; // Huffman tables read data
input[10:0] idct_in_cbus; // Data/control bus from IDCT
output[12:0] idct_out_cbus; // Data/control bus to IDCT
wire[12:0] idct_out_cbus;
input[10:0] idctbuffer_dout; // Data bus from IDCT buffer
output[29:0] idctbuffer_out_cbus; // Control/data bus to IDCT buffer
wire[29:0] idctbuffer_out_cbus;
input[7:0] qt_dout; // Q-tables data
output[18:0] qtables_out_cbus; // Control data bus to Q-tables
wire[18:0] qtables_out_cbus;
// Internal signal declarations
wire en1; // Global enable (1)
// Input fifo IF
wire[3:0] din_fifo_cbus; // Input fifo control bus
wire din_fifo_clr_1x; // Clear input fifo (slow clock domain/output)
wire din_fifo_empty; // Input fifo empty flag
wire din_fifo_full; // Input fifo full
wire din_fifo_ren; // Input fifo read enable
wire inwait_int; // Input wait (prevents reading from stream fifo)
// Q-Tables IF
wire[9:0] dqt_cbus; // Q-tables control bus
wire[1:0] tqi; // Q-Tables selector
wire e_d; // Enhanced quantization scheme selector
// Auxiliary Control/Status signals
wire ecs; // Entropy-coded scan processing flag (registered ecs_cu)
wire ecs_cu; // Entropy-coded scan processing flag
// MCU unit IF
wire[3:0] frame_himax; // Maximum horizontal subsampling factor
wire[3:0] frame_vimax; // Maximum vertical subsampling factor
wire[3:0] hi_fast; // Horizontal subsampling factor (fast)
wire[3:0] vi_fast; // Vertical subsampling factor (fast)
wire[3:0] hi_slow; // Horizontal subsampling factor (slow)
wire[3:0] vi_slow; // Vertical subsampling factor (slow)
wire[13:0] hmcu; // Horizontal MCU index
wire[13:0] vmcu; // Vertical MCU index
wire[1:0] mcu_cbus; // MCU unit control bus
wire[1:0] mcu_csj; // MCU's scan-component selector
wire sen; // Enable for latch parameters
wire[2:0] nf; // Number of components in frame
wire[15:0] x; // Number of samples in line
wire[15:0] y; // Number of lines
wire[15:0] ri; // Restart interval length
wire[2:0] ns; // Number of components in scan
// Huffman tables fifo IF
wire[1:0] htfifo_cbus; // Huffman Tables fifo control bus
wire[6:0] ht_cbus; // Huffman decoder's control bus
wire ht_fifo_clr; // Huffman Tables fifo clear
wire ht_fifo_empty; // Huffman tables fifo empty
wire ht_fifo_full; // Huffman tables fifo full
wire ht_fifo_ren; // Huffman Tables fifo read enable
wire huffd_datavalid; // Huffman decoder output valid
wire[7:0] tdin; // Huffman tables fifo ouptut data
// Huffman decoder IF
wire[31:0] huffd_din; // Huffman decoder input
wire[31:0] ecs_data; // Entropy-coded segment data
wire huffd_en; // Enable MCU unit
wire huffd_eob; // End of block flag from Huffman decoder
wire huffd_load; // Load from input fifo (drived from Huffman decoder)
wire huffd_lum_cr; // Luminance Chrominance selector
wire huffd_res; // Huffman decoder restrat flag
wire huffdclr; // Clear MCU unit
wire taj; // AC tables selector
// IDCT IF
wire idct_finished; // IDCT finshed flag
wire[1:0] idctcu_cbus; // IDCT control unit control bus
// Register file IF
wire[6:0] sof0_cbus; // SOF0 register control bus
wire[7:0] sof0ci; // Component identifier from from SOF0 marker
wire[4:0] sos_cbus; // SOS register control bus
// Implicit buffer signal declarations
wire eos_internal;
//-----------------------------------------------------------------------------
assign streamren = ~inwait_int;
//-----------------------------------------------------------------------------
// Assignments to/from control and busses data of markers parse
//-----------------------------------------------------------------------------
assign sof0ci = mp_out_common_cbus[82:75];
assign frame_himax = mp_out_common_cbus[3:0];
assign frame_vimax = mp_out_common_cbus[7:4];
assign ri = mp_out_common_cbus[23:8];
//-----------------------------------------------------------------------------
assign sof0_cbus = mp_out_d_cbus[6:0];
assign sos_cbus = mp_out_d_cbus[23:19];
assign dqt_cbus = mp_out_d_cbus[16:7];
assign htfifo_cbus[1] = mp_out_d_cbus[18] & en;
assign htfifo_cbus[0] = mp_out_d_cbus[17];
assign idctcu_cbus[1] = mp_out_d_cbus[27] & en;
assign idctcu_cbus[0] = mp_out_d_cbus[26] & en;
assign din_fifo_cbus[3] = mp_out_d_cbus[31] & en;
assign din_fifo_cbus[2] = mp_out_d_cbus[30] & en;
assign din_fifo_cbus[1] = mp_out_d_cbus[29] & en;
assign din_fifo_cbus[0] = mp_out_d_cbus[28] & en;
assign mcu_cbus[1] = mp_out_d_cbus[25] & en;
assign mcu_cbus[0] = mp_out_d_cbus[24] & en;
assign inwait_int = mp_out_d_cbus[42];
assign e_d = mp_out_d_cbus[38];
assign ecs_cu = mp_out_d_cbus[37];
assign sen = mp_out_d_cbus[39] & en;
assign soi_eoi = mp_out_d_cbus[41:40];
//-----------------------------------------------------------------------------
assign mp_in_d_cbus[0] = idct_finished;
assign mp_in_d_cbus[1] = ht_fifo_empty;
assign mp_in_d_cbus[2] = ht_fifo_full;
assign mp_in_d_cbus[3] = din_fifo_full;
//-----------------------------------------------------------------------------
assign en1 = en & hd_clk_en;
//-----------------------------------------------------------------------------
// Assert input fifo read enable, when global enable is asserted, huffman decoder is enabled,
// and huffman decoder asks for a new data
assign din_fifo_ren = huffd_en & huffd_load & en;
// Input to huffman decoder is either ecs-data (during decoding mode)
// or table specification data (during tables-programming mode)
assign huffd_din = (ecs == 1) ? ecs_data : {ecs_data[31:8], tdin};
// Clear read register of input fifo, whenever huffman decoder is cleared
assign din_fifo_clr_1x = (huffdclr | htfifo_cbus[0]) & en;
// Instance port mappings.
din_fifo u_din_fifo (
.clk(clk),
.hd_clk_en(hd_clk_en),
.clrx1(din_fifo_clr_1x),
.clrx4(din_fifo_cbus[1]),
.din(streamdin),
.en(en),
.flush(din_fifo_cbus[3]),
.ren(din_fifo_ren),
.rst(rst),
.wen(din_fifo_cbus[2]),
.dout(ecs_data),
.empty(din_fifo_empty),
.full(din_fifo_full)
);
ecs_data_processor u_ecs_data_processor (
.clk(clk),
.hd_clk_en(hd_clk_en),
.en(en),
.rst(rst),
.clr(clr),
.csj(mcu_csj),
.din_fifo_empty(din_fifo_empty),
.ecs(ecs),
.eos(eos_internal),
.ps_fifo_in_cbus(ps_fifo_in_cbus),
.dht_raddr(dht_raddr),
.dht_dout(dht_dout),
.ps_fifo_out_cbus(ps_fifo_out_cbus),
.huffd_run_program(ht_cbus[6]),
.huffd_cu_en(mcu_cbus[1]),
.huffd_res(huffd_res),
.huffd_din(huffd_din),
.huffd_cu_clr(mcu_cbus[0]),
.huffd_lum_cr(huffd_lum_cr),
.huffd_code_symbol(ht_cbus[5]),
.huffd_en_w(ht_cbus[1]),
.huffd_clr_w(ht_cbus[0]),
.huffd_use_ac_dc(ht_cbus[3]),
.huffd_ac_dc(ht_cbus[4]),
.huffdclr(huffdclr),
.huffd_eob(huffd_eob),
.huffd_load(huffd_load),
.huffd_datavalid(huffd_datavalid),
.huffden_r(huffd_en),
.idct_buffdout(idctbuffer_dout),
.idctbuffer_out_cbus(idctbuffer_out_cbus),
.idct_in_cbus(idct_in_cbus),
.idct_cu_clr(idctcu_cbus[0]),
.idct_cu_en(idctcu_cbus[1]),
.idct_finished(idct_finished),
.idct_out_cbus(idct_out_cbus),
.qt_din(streamdin),
.qt_dout(qt_dout),
.qt_en_w(dqt_cbus[0]),
.qt_tq_w(dqt_cbus[9:8]),
.qt_wen(dqt_cbus[1]),
.tqi(tqi),
.ns(ns),
.e_d(e_d),
.qt_addr_w(dqt_cbus[7:2]),
.qtables_out_cbus(qtables_out_cbus),
.pixout_rdy(pixout_rdy),
.pixout(pixout),
.pixout_eob(pixout_eob),
.pixout_lbs(pixout_lbs),
.pixout_sob(pixout_sob),
.pixout_wen(pixout_wen)
);
ht_fifo u_ht_fifo (
.clk(clk),
.hd_clk_en(hd_clk_en),
.clrx1(htfifo_cbus[0]),
.clrx4(htfifo_cbus[0]),
.din(streamdin),
.en(en),
.ren(ht_fifo_ren),
.rst(rst),
.wen(htfifo_cbus[1]),
.dout(tdin),
.empty(ht_fifo_empty),
.full(ht_fifo_full)
);
huffman_d_tables_cu u_huffman_d_tables_cu (
.clk(clk),
.clr(htfifo_cbus[0]),
.din(tdin),
.en(en),
.hd_clk_en(hd_clk_en),
.ht_fifo_empty(ht_fifo_empty),
.ht_fifo_full(ht_fifo_full),
.rst(rst),
.ht_cbus(ht_cbus),
.ht_fifo_clr(ht_fifo_clr),
.ht_fifo_ren(ht_fifo_ren)
);
jdreg_1 ecsdreg (
.clk(clk),
.d(ecs_cu),
.en(en1),
.rst(rst),
.q(ecs)
);
jdreg_1 scanactivereg (
.clk(clk),
.d(ecs_cu),
.en(en),
.rst(rst),
.q(scanactive)
);
mcuunit u_mcuunit (
.clk(clk),
.clrx1(huffdclr),
.clrx4(mcu_cbus[0]),
.en(huffd_en),
.frame_himax(frame_himax),
.frame_vimax(frame_vimax),
.hd_clk_en(hd_clk_en),
.hi_fast(hi_fast),
.hi_slow(hi_slow),
.huffd_datavalid(huffd_datavalid),
.huffd_eob(huffd_eob),
.ns(ns),
.ri(ri),
.rst(rst),
.sen(sen),
.vi_fast(vi_fast),
.vi_slow(vi_slow),
.x(x),
.y(y),
.eos(eos_internal),
.hmcu(hmcu),
.huffd_res(huffd_res),
.mcu_csj(mcu_csj),
.vmcu(vmcu)
);
mux_1 lumchrmux (
.a(ht_cbus[2]),
.b(taj),
.s(ecs),
.y(huffd_lum_cr)
);
registerfile u_registerfile (
.clk(clk),
.din(streamdin),
.mcu_csj(mcu_csj),
.rst(rst),
.sof0_rf_addr(sof0_cbus[6:4]),
.sof0_rf_ci_w(sof0_cbus[3:2]),
.sof0_rf_clr(sof0_cbus[0]),
.sof0_rf_wen(sof0_cbus[1]),
.sos_rf_clr(sos_cbus[0]),
.sos_rf_csj(sos_cbus[3:2]),
.sos_rf_waddr(sos_cbus[4]),
.sos_rf_wen(sos_cbus[1]),
.ci_out(),
.hi_fast(hi_fast),
.hi_slow(hi_slow),
.nf(nf),
.ns(ns),
.p(),
.taj(taj),
.tdj(),
.tqi(tqi),
.vi_fast(vi_fast),
.vi_slow(vi_slow),
.x(x),
.y(y)
);
// Implicit buffered output assignments
assign eos = eos_internal;
endmodule