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本来打算自己用表征以下标准单元,验证以下里流程,现在出现如下问题,无法进行下去。
elc> source step1.tcl
Database : foo is now opened
set_var EC_SPICE_SIMPLIFY = 1
set_var EC_HALF_WIDTH_HOLD_FLAG = 1
set_var EC_SIM_NAME = spectre
set_var EC_SIM_TYPE = spectre
set_var EC_SPICE_SUPPLY1_NAMES = VDD
set_var EC_SPICE_SUPPLY0_NAMES = VSS
==== Simplify Mode ====
MODEL FILE: model.m ( #size = 233187 )
Reading MODEL: NCH
Reading MODEL: PCH
Reading MODEL: NCHMIS in SUBCKT: NCH_MIS
Reading MODEL: PCHMIS in SUBCKT: PCH_MIS
SUBCKT FILE: model.m ( #size = 233187 )
Reading SUBCKT:NCH_MIS
Reading SUBCKTCH_MIS
SUBCKT FILE: NANDX1.scs ( #size = 631 )
Reading SUBCKT:NAND2X1
Expanding SUBCKT:NAND2X1
Writing : foo.ipdb/NAND2X1.design
Writing : foo.ipdb/NAND2X1.design/body/path
Writing : foo.ipdb/NAND2X1.design/body/instance
Writing : foo.ipdb/NAND2X1.design/body/net
Writing : foo.ipdb/NAND2X1.design/boundary/port
Writing : foo.ipdb/NCH.device
Writing : foo.ipdb/NCH.device/boundary/port
Writing : foo.ipdb/PCH.device
Writing : foo.ipdb/PCH.device/boundary/port
Reading : foo.ipdb/NAND2X1.design
==============================
DESIGN : NAND2X1
==============================
----------------------------------
A B : Y
----------------------------------
D0000: R 1 : F : DELAY(A)
D0001: R 0 : 1 : POWER(A)
D0002: F 1 : R : DELAY(A)
D0003: F 0 : 1 : POWER(A)
D0004: 1 R : F : DELAY(B)
D0005: 0 R : 1 : POWER(B)
D0006: 1 F : R : DELAY(B)
D0007: 0 F : 1 : POWER(B)
----------------------------------
=> 8 vectors generated
Writing : foo.ipdb/NAND2X1.design/simulate/spec
Writing : foo.ipdb/NAND2X1.design/simulate/subckt
Writing : foo.ipdb/NAND2X1.design/boundary/port
Writing : foo.ipdb/NAND2X1.design/body/type
================================
stimulus generation summary
================================
Name #MOS #DVEC #RVEC
----------------------------------------
NAND2X1 4 8 0
----------------------------------------
8 0
Reading setup file : setup.ss
elc> db_gate
==============================
DESIGN : NAND2X1
==============================
DESIGN ( NAND2X1 );
// =================
// PORT DEFINITION
// =================
INPUT A ( A );
INPUT B ( B );
OUTPUT Y ( Y );
SUPPLY0 VSS ( VSS );
SUPPLY1 VDD ( VDD );
// ===========
// INSTANCES
// ===========
NAND ( Y, A, B );
END_OF_DESIGN;
elc> db_close
Database : foo is closed
elc> source step2.tcl
Database : foo is now opened
set_var EC_SIM_USE_LSF = 1
set_var EC_SIM_LSF_CMD =
set_var EC_SIM_NAME = spectre
set_var EC_SIM_TYPE = spectre
set_var EC_SPICE_SUPPLY1_NAMES = VDD
set_var EC_SPICE_SUPPLY0_NAMES = VSS
set_var EC_HALF_WIDTH_HOLD_FLAG = 1
DESIGN PROCESS #ID STATUS IPDB
-------------+-------------+----------+--------------+-----------
[WARNING(db_spice)]No spice simulation to do, please check the cell/process list for any error
Database : foo is closed
Memory : 3.00M
Time : 0.54 (user), 0.02 (sys), 0.56 (cpu), 1772.71 (real)
貌似意思是没有仿真可以可以做,可是确实已经生成了vector,这是foo.ipdb中的spec文件
DESIGN(NAND2X1) + REFERENCE(NCH,PCH);
PORT(A) + DIRECTION(INPUT) + NET_NUMBER(0);
PORT(B) + DIRECTION(INPUT) + NET_NUMBER(1);
PORT(Y) + DIRECTION(OUTPUT) + LOGIC(~(A&B)) + FALL(-NAN,-NAN) + NET_NUMBER(2);
PORT(VDD) + DIRECTION(INPUT) + SUPPLY1 + BULK + NET_NUMBER(3);
PORT(VSS) + DIRECTION(INPUT) + SUPPLY0 + BULK + NET_NUMBER(4);
ARC(A:Y) + NEGATIVE_UNATE + ONE_STAGE
+ TRAN(10:01)
+ TRAN(01:10)
+ USE(D0000,D0002);
ARC(B:Y) + NEGATIVE_UNATE + ONE_STAGE
+ TRAN(10:01)
+ TRAN(01:10)
+ USE(D0004,D0006);
VECTOR(R1D10) + ID(D0000) + MID(MD0000) + DELAY(A) + TARGET(Y);
VECTOR(R0H10) + ID(D0001) + MID(MP0001) + POWER(A);
VECTOR(F1U10) + ID(D0002) + MID(MD0000) + DELAY(A) + TARGET(Y);
VECTOR(F0H10) + ID(D0003) + MID(MP0001) + POWER(A);
VECTOR(1RD10) + ID(D0004) + MID(MD0004) + DELAY(B) + TARGET(Y);
VECTOR(0RH10) + ID(D0005) + MID(MP0005) + POWER(B);
VECTOR(1FU10) + ID(D0006) + MID(MD0004) + DELAY(B) + TARGET(Y);
VECTOR(0FH10) + ID(D0007) + MID(MP0005) + POWER(B);
END_OF_DESIGN;
是软件破解失败的问题,还是我做错了哪一步?求教了 |
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