DFT仿真问题求教

tigerajs

TETRAMAX产生测试向量，使用ncverilog进行仿真，不带任何timing时序信息，结果仿真报错，不知道什么原因，谢谢

xhf811

这样问问题，别人是帮不了你的！

tigerajs

仿真时报出error:
// *** ERROR during scan pattern 0 (detected during load of pattern 1)
  0 1 0 (exp=1, got=0)  // pin scan_so, scan cell 0, T=      957240.00 ns
  0 1 2 (exp=0, got=1)  // pin scan_so, scan cell 2, T=      957440.00 ns
  0 1 4 (exp=1, got=0)  // pin scan_so, scan cell 4, T=      957640.00 ns
  0 1 6 (exp=0, got=1)  // pin scan_so, scan cell 6, T=      957840.00 ns
  0 1 8 (exp=1, got=0)  // pin scan_so, scan cell 8, T=      958040.00 ns
  0 1 10 (exp=0, got=1)  // pin scan_so, scan cell 10, T=      958240.00 ns
  0 1 12 (exp=1, got=0)  // pin scan_so, scan cell 12, T=      958440.00 ns
  0 1 14 (exp=0, got=1)  // pin scan_so, scan cell 14, T=      958640.00 ns
  0 1 16 (exp=1, got=0)  // pin scan_so, scan cell 16, T=      958840.00 ns
  0 1 18 (exp=0, got=1)  // pin scan_so, scan cell 18, T=      959040.00 ns
  0 1 20 (exp=1, got=0)  // pin scan_so, scan cell 20, T=      959240.00 ns
  0 1 22 (exp=0, got=1)  // pin scan_so, scan cell 22, T=      959440.00 ns
  0 1 24 (exp=1, got=0)  // pin scan_so, scan cell 24, T=      959640.00 ns
  0 1 26 (exp=0, got=1)  // pin scan_so, scan cell 26, T=      959840.00 ns
  0 1 28 (exp=1, got=0)  // pin scan_so, scan cell 28, T=      960040.00 ns
  0 1 30 (exp=0, got=1)  // pin scan_so, scan cell 30, T=      960240.00 ns
  0 1 32 (exp=1, got=0)  // pin scan_so, scan cell 32, T=      960440.00 ns
  0 1 34 (exp=0, got=1)  // pin scan_so, scan cell 34, T=      960640.00 n

用tetramax产生测试向量报出：

Warning: There were 630 faultable pins lost due to tied gate optimizations. (M126)
There were 129015 primitives and 2434 faultable pins removed during model optimizations
Warning: Rule B7 (undriven module output pin) was violated 605 times.
Warning: Rule B8 (unconnected module input pin) was violated 1090 times.
Warning: Rule B9 (undriven module internal net) was violated 201 times.
Warning: Rule B10 (unconnected module internal net) was violated 754 times.
Warning: Rule N16 (overspecified UDP) was violated 1 times.
Warning: Rule N23 (inconsistent UDP) was violated 1 times

run_atpg basic_scan_only
***********************************************************
*  NOTICE:  The following DRC violations were previously  *
*  encountered. The presence of these violations is an    *
*  indicator that it is possible that the ATPG patterns   *
*  created during this process may fail in simulation.    *
*                                                         *
*  Rules:  N23                                            *
**********************************************************
不知道具体怎么修改

otogyg

回复 1# tigerajs


    你的意思是没有反标时序，用的库里面的延时信息？

    不知道你delay_mode 有没有设置。

tigerajs

没有加任何时序,VCS加了nospecify

otogyg

回复 5# tigerajs


    1，你随便找个cell，看仿真的波形，确认有没有时序信息。
    2，TMAX里有没有自己仿真？（run_simulation）

tigerajs

看了下，没有时序延迟的，TMAX仿真通过的，可以加我qq吗

manson8252

xiang dajia xuexie

xiaonaldo

可以在design brower 查看一个单元的波形图，看看是不是有时序反标所导致的问题。再从schematic中去分析原因。

tigerajs

没有时序的，现在scan_cell5000多才有错误。一个有9000链