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Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications
a b s t r a c t
To meet the desired electrostatic discharge (ESD) robustness, ESD diodes was added into the I/O cells of
integrated circuits (ICs). However, the parasitic capacitance from the ESD diodes often caused degradation
on circuit performance, especially in the high-speed I/O applications. In this work, two modified layout
styles to effectively improve the figures of merits (FOMs) of ESD protection diodes have been
proposed, which are called as multi-waffle and multi-waffle-hollow layout styles. Experimental results
in a 90-nm CMOS process have confirmed that the FOMs (RON CESD, ICP/CESD, VHBM/CESD, and ICP/ALayout)
of ESD protection diodes with new proposed layout styles can be successfully improved.
2011 Elsevier Ltd. All rights reserved. |
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