[AMD社招] 最新招聘2011/11/24(工作地点：上海/北京，员工内荐)

nospecial

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今天HR刚刚open的新职位，一共是25个上海的职位和3个北京的职位，涵盖了IC硬件和软件以及其它部门的职位。下面列出了职位的简单信息和工作地址，JD详见附件（若无法下载，可直接mail或者QQ索要你所关心职位的JD）。

PS：这次只面向社招，只能对今年毕业的童鞋们表示遗憾了。[url=mailto:有兴趣的同志们可以把简历直接mail我的邮箱luyuanshan9@hotmail.com，或者QQ细聊]有兴趣的同志们可以把简历直接mail我的邮箱luyuanshan9@hotmail.com，或者QQ细聊[/url] : 25863883

No.
Job Title                           
Location

1
MTS/Sr. GPU Firmware Engineer
Shanghai

2
MTS - PCB Layout Engineer
Shanghai

3
Sr. Memory Tuning Engineer
Shanghai

4
MTS/Sr. Graphic Board Design Engineer
Shanghai

5
MTS/Sr. System Debug Engineer - Board Design
Shanghai

6
MTS/Sr. System Debug Engineer - Linux Kernel
Shanghai

7
MTS/Sr. System Debug Engineer – Silicon
Shanghai

8
MTS/Sr. Elec. Analysis & Design (Silicon Validation) Shanghai

9
Sr. Validation Engineer - SI            
Shanghai

10
MTS/Sr. Physical Design Engineer            
Shanghai

11
MTS/Sr. ASIC Design Verification Engineer - GateSim Shanghai

12
MTS/Sr. Performance Verification Engineer
Shanghai

13
MTS/Sr. System Design Verification Engineer
Shanghai

14
MTS/Sr. Design Verification Engineer for Graphics Hardware Shanghai

15
Sr.  Engineer of GPU IP
Shanghai

16
MTS/ Sr. DFX Team Engineer
Shanghai

17
SMTS/MTS/ Sr. DV Engineer
Shanghai

18
MTS/Sr. Linux  Driver
Shanghai

19
MTS/Sr. BIOS         
Shanghai

20
MTS/Sr. Open GL         
Shanghai

21
MTS/Sr. Windows D3D
Shanghai

22
Program Manager for SW
Shanghai

23
MTS of Application software engineer
Shanghai

24
MTS/Sr. Windows 2d Graphic Driver
Shanghai

25
Finance Manager         
Shanghai

26
Sr. FEINT Eng (DV)
Beijing

27
Senior Layout Eng (Sr. PD)
Beijing

28
Sr. Verification Eng (Sr. DV)
Beijing

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回复 1# nospecial


    顶一下！

yohuang

刚裁员，又开始招人， 明显是内部势力范围重组

nospecial

新增添了一个职位，这次要求较低，刚刚工作不久打算换个环境或者换个方向的请多关注(社招，非毕业生招聘)：
29    ASIC CAD Engineer                    Shanghai
  
DESCRIPTION OF DUTIES:
1.Participate in the design and implementation of the leading edge, front-to-back ASIC design flow which covers logical and physical implementation and analysis of complex devices that integrate multiple cores and IP’s from organizations with AMD global teams.
2.Participate in the research of Design Methodology to improve automation and  productivity to produce AMD's new high-quality cutting-edge graphics processing products
3.Technical support and programming
4.Interface with EDA venders
  
PREFERRED EXPERIENCE:
1.major in EE, CS, Physics or related, Master with 1+ years or Bachelor with 3+ years working experiences
2.good programming skill with one or more languages (e.g. tcl, perl , python, c/c++, etc) in unix/linux and a strong desire to automate flow
3.experience in ASIC design (digital design, Front-end or Back-end), experience with VerilogHDL coding
4.experience in one or more ASIC flows (logic synthesis, STA, formality check, Design for Power, place & route, signal integrity analysis, CTS design, design rule and connectivity verification, DFT ) and usage of related EDA tools
5.Good written and spoken English
6.Good communication skills and be able to work both independently and in a team