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ESD Protection Design With Lateral DMOS
Transistor in 40-V BCD Technology
Chang-Tzu Wang, Student Member, IEEE, and Ming-Dou Ker, Fellow, IEEE
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 12, DECEMBER 2010
Abstract—An electrostatic discharge (ESD) protection design
for smart power applications with lateral double-diffused MOS
(LDMOS) transistors is investigated. With the gate-driven and
substrate-triggered circuit techniques, the n-channel LDMOS
can be quickly turned on to protect the output drivers during
an ESD stress event. The proposed gate-driven and substratetriggered
ESD protection circuits have been successfully verified
in a 0.35-μm 5 V/40 V bipolar CMOS DMOS (BCD) process,
which can sustain ESD voltages of 4 kV in human-body-model
(HBM) and 275 V in machine-model (MM) ESD tests. In addition,
the power-rail ESD protection design can also be achieved with
a stacked structure to protect 40-V power pins without a latchup
issue in the smart power integrated circuits.
Index Terms—Bipolar CMOS DMOS (BCD) process, electrostatic
discharge (ESD), ESD protection, latchup. |
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发表于 2011-10-5 21:14:28
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