PHYSICAL DESIGN TECHNIQUES OF A MULTI-PROTOCOL SERDES PHY

immonster · 发表于 2011-8-24 10:24:49

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ABSTRACT
In recent years, high-speed serial links (SERDES) have become popular. In the personal computer market, examples include PCI-Express (2.5Gbps) and SATA (1.5-3Gbps). Furthermore, XAUI (3.125Gps) has gained popularity as an ASIC interface. This paper covers a physical layer, multi-protocol IP (PHY) that handles the aforementioned protocols. While the analog physical design was challenging, so too was the digital physical design. Select digital physical design techniques are covered in this paper. The results are a fully functional 130nm PHY and a 90nm PHY.

etopyes8 · 发表于 2011-8-24 17:17:57

Thanks for your information......................
Thanks....................

floatice · 发表于 2011-8-27 10:07:32

have a look!

gaojun927 · 发表于 2011-8-29 13:23:24

好东西啊

accel30 · 发表于 2012-8-24 22:38:13

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accel30 · 发表于 2012-8-24 22:39:25

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nareshreddy · 发表于 2013-7-1 23:31:42

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yesterdaym240 · 发表于 2013-12-22 11:55:32

下来看看

kim_mechane · 发表于 2014-4-9 21:30:52

谢谢分享！~~

木子11 · 发表于 2014-11-21 10:30:18

下来看看。。

[资料] PHYSICAL DESIGN TECHNIQUES OF A MULTI-PROTOCOL SERDES PHY

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