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楼主 |
发表于 2011-7-31 12:51:09
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把ligrd -c的东西也放上来了
21:43:33 (lmgrd) -----------------------------------------------
21:43:33 (lmgrd) Please Note:
21:43:33 (lmgrd)
21:43:33 (lmgrd) This log is intended for debug purposes only.
21:43:33 (lmgrd) In order to capture accurate license
21:43:33 (lmgrd) usage data into an organized repository,
21:43:33 (lmgrd) please enable report logging. Use Macrovision's
21:43:33 (lmgrd) software license administration solution,
21:43:33 (lmgrd) FLEXnet Manager, to readily gain visibility
21:43:33 (lmgrd) into license usage data and to create
21:43:33 (lmgrd) insightful reports on critical information like
21:43:33 (lmgrd) license availability and usage. FLEXnet Manager
21:43:33 (lmgrd) can be fully automated to run these reports on
21:43:33 (lmgrd) schedule and can be used to track license
21:43:33 (lmgrd) servers and usage across a heterogeneous
21:43:33 (lmgrd) network of servers including Windows NT, Linux
21:43:33 (lmgrd) and UNIX. Contact Macrovision at
21:43:33 (lmgrd) www.macrovision.com for more details on how to
21:43:33 (lmgrd) obtain an evaluation copy of FLEXnet Manager
21:43:33 (lmgrd) for your enterprise.
21:43:33 (lmgrd)
21:43:33 (lmgrd) -----------------------------------------------
21:43:33 (lmgrd)
21:43:33 (lmgrd)
21:43:33 (lmgrd) The license server manager (lmgrd) running as root:
21:43:33 (lmgrd) This is a potential security problem
21:43:33 (lmgrd) and is not recommended.
[root@localhost ~]# 21:43:33 (lmgrd) FLEXnet Licensing (v10.8.5.0 build 31891 i86_re3) started on localhost.localdomain (linux) (7/30/2011)
21:43:33 (lmgrd) Copyright (c) 1988-2006 Macrovision Europe Ltd. and/or Macrovision Corporation. All Rights Reserved.
21:43:33 (lmgrd) US Patents 5,390,297 and 5,671,412.
21:43:33 (lmgrd) World Wide Web: http://www.macrovision.com
21:43:33 (lmgrd) License file(s): /root/synopsys/license/synopsys.dat
21:43:33 (lmgrd) lmgrd tcp-port 27000
21:43:33 (lmgrd) Starting vendor daemons ...
21:43:33 (lmgrd) Started snpslmd (internet tcp_port 41799 pid 4832)
21:43:33 (snpslmd) FLEXnet Licensing version v10.8.5.3 build 59306 i86_re3
21:43:34 (snpslmd) Synopsys Corporate Licensing (SCL) Release: version SCL_10.9.3
21:43:34 (snpslmd) Server started on localhost.localdomain for: SSS
21:43:34 (snpslmd) SABER_GUIDE Galaxy-DFY Galaxy-Beta
21:43:34 (snpslmd) Galaxy-Internal-Only PrimeTime-New-Technology Galaxy-ICC
21:43:34 (snpslmd) PrimeRail Power-Optimization-Beta1 Power-Optimization-Beta2
21:43:34 (snpslmd) Formality-Beta1 Formality-Beta2 Galaxy-MV
21:43:34 (snpslmd) STAR-RC2_MANAGER Galaxy-MCMM PrimeTime-PX
21:43:34 (snpslmd) DB-Mode DC-Topographical snps_fs_nwave
21:43:34 (snpslmd) Pathmill-migrate Pathmill-plus-migrate primerail_hsim
21:43:34 (snpslmd) NanoTime-ultra Galaxy-CCS pathmill
21:43:34 (snpslmd) pathmill_plus amps Galaxy_FP_Beta
21:43:34 (snpslmd) Galaxy_MultiRoute4 Galaxy_MultiRoute8 PrimeTime-VX
21:43:34 (snpslmd) Galaxy-AdvRules Galaxy-FlipChip Galaxy-AdvCTS
21:43:34 (snpslmd) Galaxy-FP-Hier Test-SDD-Timing Galaxy-AdvTech
21:43:34 (snpslmd) Galaxy-AdvOpt Galaxy-CTMesh Galaxy-Zroute
21:43:34 (snpslmd) Test-Power Test-Physical DCT-Congestion
21:43:34 (snpslmd) DCT-GUI DC-Extension Galaxy-FP-MV
21:43:34 (snpslmd) Galaxy-FP-AdvCTS Galaxy-FP-AdvTech NCX
21:43:34 (snpslmd) Galaxy-SPG PrimeTime-PX-Statistical PrimeTime-PX-New-Technology
21:43:34 (snpslmd) PrimeRail-New-Technology PrimeRail-static PrimeRail-adv
21:43:34 (snpslmd) Test-CompressionPlus-Syn Test-CompressionPlus-ATPG NCX-addon
21:43:34 (snpslmd) him_sml him_sml BC-FPGA
21:43:34 (snpslmd) SC-FPGA DC-Ultra example_feature
21:43:34 (snpslmd) leda-mx Test-LBIST-ATPG DC-FPGA-Features
21:43:34 (snpslmd) Test-DFTC-TMAX PhysOpt-Hierarchy PhysOpt-Onroute
21:43:34 (snpslmd) PhysOpt-Parallel PhysOpt-SI Primepower
21:43:34 (snpslmd) Primepower_gui TurboWave DC-FPGA-Add-On
21:43:34 (snpslmd) DC-FPGA-Accelerator DC-XG PhysOpt-ClockTree
21:43:34 (snpslmd) PhysOpt-Extraction PhysOpt-Routing RouteCompiler
21:43:34 (snpslmd) fpc_foundation fpc_pna fpc_utils
21:43:34 (snpslmd) fpc_special1 fpc_special2 fpc_special3
21:43:34 (snpslmd) Test-Validate Test-Accelerate-Max Formality-DV
21:43:34 (snpslmd) chiparch_migrate planet_migrate DesignWare-ARMCORES-tlm
21:43:34 (snpslmd) DesignWare-AMBA-tlm Test-LBIST-Integration VHDL-Compiler-Presto
21:43:34 (snpslmd) primepower_vcd Test-Beta-7 Test-Beta-8
21:43:34 (snpslmd) Test-Beta-9 Test-STDVR Test-MBIST-Integration
21:43:34 (snpslmd) HDL-Compiler-SystemVerilog primepower_beta MV-Opt
21:43:34 (snpslmd) PhysOpt-VH Formality-TX Formality-Distributed
21:43:34 (snpslmd) PhysOpt-Integration PhysOpt-Route PhysOpt-Beta-Milkyway
21:43:34 (snpslmd) PhysOpt-Beta-SI PhysOpt-Beta-CTS PhysOpt-Beta-Route
21:43:34 (snpslmd) PhysOpt-Route-TD Milkyway-Interface Test-Fault-Max
21:43:34 (snpslmd) PAW PsynGui-ChipMap Formality-ESP
21:43:34 (snpslmd) PhysOpt-XG PsynGui-AARender DC-FPGA-Add-On-to-DC
21:43:34 (snpslmd) Test-Compression-ATPG Test-Compression-Synthesis HDL-Compiler-Old
21:43:34 (snpslmd) VHDL-Compiler-Old Test-Mbist-Program Test-Mbist-Bitstream
21:43:34 (snpslmd) Galileo Galileo-PSYN Galileo-PnR
21:43:34 (snpslmd) Galileo-GUI NanoTime NanoTime-PathMill-Shared
21:43:34 (snpslmd) Galileo-Internal-Only PhysOpt-MV Astro-MV
21:43:34 (snpslmd) Galaxy-PSYN Galaxy-PNR Galaxy-Common
21:43:34 (snpslmd) Galaxy-GUI-PSYN Galaxy-GUI-PNR Galaxy-FP
21:43:34 (snpslmd) Galaxy-Power Galaxy-IU Galaxy-DFT
21:43:34 (snpslmd) Galaxy-Prototype DesignWare-MPEG2-VDEC-Source DesignWare-MPEG2
21:43:34 (snpslmd) DesignWare-MPEG2-Source DesignWare-SystemIO DesignWare-SystemIO-Source
21:43:34 (snpslmd) DesignWare-USB DesignWare-USB-Source DesignWare-USB2
21:43:34 (snpslmd) DesignWare-USB2-Source DesignWare-1394 DesignWare-1394-Source
21:43:34 (snpslmd) DesignWare-ETHERNET DesignWare-ETHERNET DesignWare-ETHERNET-Source
21:43:34 (snpslmd) DesignWare-MemoryBist DesignWare-MemoryBist-Source COSSAP_amr
21:43:34 (snpslmd) DCExpert-PrimeTime PrimeTime-SI PrimeTime-SI
21:43:34 (snpslmd) RTL-Power-Analysis DesignWare-MPEG DesignWare-MPEG-Source
21:43:34 (snpslmd) DesignWare-TCA DesignWare-TCA-Source DesignWare-BIST
21:43:34 (snpslmd) DesignWare-BIST-Source SC-BC SC-RTL
21:43:34 (snpslmd) Formality-Transit Formality-E1 Test-Map
21:43:34 (snpslmd) Test-Compile-Max Test-Compile-Share Test-ATPG-Max
21:43:34 (snpslmd) Test-Beta-3 Test-Beta-4 Test-Beta-5
21:43:34 (snpslmd) Test-Beta-6 Test-CA-2 Test-CA-3
21:43:34 (snpslmd) Test-CA-4 Test-PR-1 Test-PR-2
21:43:34 (snpslmd) Test-PR-3 Test-PR-4 route66
21:43:34 (snpslmd) encore HLS-SystemC HLS-FPGA-SystemC
21:43:34 (snpslmd) CoCentric-SYS-DesignCenter CoCentric-SYS-Simulator CoCentric-SYS-Davis
21:43:34 (snpslmd) CoCentric-SYS-HWSimIF CoCentric-SYS-HWflow COSIM-SRO
21:43:34 (snpslmd) COSIM-VCS COSIM-MTI COSIM-VXL
21:43:34 (snpslmd) COSIM-LFG COSIM-NCV CoCentric-FXD-Interpolator
21:43:34 (snpslmd) CoCentric-FXD-GUI CoCentric-FXD-Simulation CoCentric-SYS-RDK-adsl
21:43:34 (snpslmd) MC-Retime MC-Retime DC64
21:43:34 (snpslmd) Constraint_Translation CoCentric-SYS-RDK-cdma2000 Formality-TransForm
21:43:34 (snpslmd) DesignWare-6811-Source FPGA-Express-MERCURY-Optimizer coreSynthesis
21:43:34 (snpslmd) coreAssembler coreBuilder coreConsultant
21:43:34 (snpslmd) SC-HLS CoCentric-SYS-RDK-docsis SC-COSIM
21:43:34 (snpslmd) PS_CTS PS_Noise_Optimization PS_Extraction
21:43:34 (snpslmd) Test-RTL-Tristate DesignWare DesignWare
21:43:34 (snpslmd) FPGA-Express-APEX2-Optimizer Test-CTL-Model Test-Core-Wrapper
21:43:34 (snpslmd) Test-Core-Integration Test-LBIST-Synthesis PhysOpt-Beta
21:43:34 (snpslmd) COSSAP_vsiccg_cyc COSSAP_vsiccg_mti COSSAP_vsiccg_vcs
21:43:34 (snpslmd) COSSAP_vsiccg_vlgxl COSSAP_vsivcg COSSAP_vsivcg_vlgxl
21:43:34 (snpslmd) COSSAP_xdcg COSSAP_xvcg COSSAP_xvsi
21:43:34 (snpslmd) Fridge-GUI Fridge-Simulation Fridge-Interpolator
21:43:34 (snpslmd) FPGA-Express FPGA-Express-32OODx-Optimizer FPGA-Express-A1200XL-Optimizer
21:43:34 (snpslmd) FPGA-Express-A1400-Optimizer FPGA-Express-A3200DX-Optimizer FPGA-Express-A42MX-Optimizer
21:43:34 (snpslmd) FPGA-Express-A54SX-Optimizer FPGA-Express-Constraint-Mgr FPGA-Express-EPF10k-Optimizer
21:43:34 (snpslmd) FPGA-Express-EPF6k-Optimizer FPGA-Express-EPF8k-Optimizer FPGA-Express-EPM7k-Optimizer
21:43:34 (snpslmd) FPGA-Express-EPM9k-Optimizer FPGA-Express-ORCA2-Optimizer FPGA-Express-ORCA3-Optimizer
21:43:34 (snpslmd) FPGA-Express-Open-Optimizer FPGA-Express-VHDL-Base FPGA-Express-VHDL-Training
21:43:34 (snpslmd) FPGA-Express-VIRTEX-Optimizer FPGA-Express-VLOG-Base FPGA-Express-XC3k-Optimizer
21:43:34 (snpslmd) FPGA-Express-XC4k-Optimizer FPGA-Express-XC5k-Optimizer FPGA-Express-XC9k-Optimizer
21:43:34 (snpslmd) FPGA-Express-GAT Formality CBA-Logical-DS
21:43:34 (snpslmd) CBA-Logical-MA CBA-Physical-DS CBA-Physical-MA
21:43:34 (snpslmd) CBA-Frame CBA-Blk-Import CBA-Blk-Export
21:43:34 (snpslmd) CBA-Transport CBA-ApolloGA-Interface CBA-CadenceSE-Interface
21:43:34 (snpslmd) ProMA-L1 ProMA-L2 ProMA-LD
21:43:34 (snpslmd) ProMA-P1 ProMA-P2 PSG-SDE
21:43:34 (snpslmd) CBA-DS-Beta ProMA-PD COSSAP_ddk_dsp16000
21:43:34 (snpslmd) COSSAP_adsl COSSAP_vsiccg_mtivlg Test-RTL-Check
21:43:34 (snpslmd) DW-IP-DEBUG electromigration_drc electromigration_drc
21:43:34 (snpslmd) ACS PhysOpt PhysOpt-Ultra
21:43:34 (snpslmd) PhysOpt-GUI BOA-BRT DesignWare-VERA
21:43:34 (snpslmd) VHDL-Event-Sim VHDL-Elaborator VHDL-Cycle-Sim
21:43:34 (snpslmd) VHDL-ScSim VHDL-VirSim ELGRECO_DesignCenter
21:43:34 (snpslmd) ELGRECO_Simulator ELGRECO_Davis Design-Vision
21:43:34 (snpslmd) FPGA-Express-EP20k-Optimizer FPGA-Express-isp1K-Optimizer FPGA-Express-isp2K-Optimizer
21:43:34 (snpslmd) FPGA-Express-isp3K-Optimizer FPGA-Express-isp5K-Optimizer FPGA-Express-isp6K-Optimizer
21:43:34 (snpslmd) FPGA-Express-isp8K-Optimizer FPGA-Express-APROA-Optimizer FCII-Altera-Edition
21:43:34 (snpslmd) DesignWare-PCI-X DesignWare-PCI-X-Source DesignWare-MPEG2-VDEC
21:43:34 (snpslmd) Test-Analysis Test-Format Test-ScanRoute
21:43:34 (snpslmd) Test-Library Test-DFT-Top Test-Compile
21:43:34 (snpslmd) Test-Compile-Remodel Test-Analysis-RTL Test-Analysis-GUI
21:43:34 (snpslmd) Test-Mbist Test-Mbist-DRAM Test-Mbist-CAM
21:43:34 (snpslmd) Test-Mbist-FLASH Test-Mbist-Diagnosis Test-Mbist-Multiport
21:43:34 (snpslmd) Test-Mbist-Algorithm Test-ATPG-PRO Test-ATPG-XP
21:43:34 (snpslmd) Test-ATPG-Limited Test-ATPG-30 Test-ATPG-Ultra
21:43:34 (snpslmd) Test-Delay Test-Faultsim Test-Diagnosis
21:43:34 (snpslmd) Test-Accelerator Test-Faultsim-8L Test-Eval
21:43:34 (snpslmd) Test-Beta Test-CA Test-Beta-2
21:43:34 (snpslmd) DesignWare-Foundation-Ultra VHMC-GenUnlocked VHMC-Eval
21:43:34 (snpslmd) VHMC-Runtime COSSAP_adpcm COSSAP_arm
21:43:34 (snpslmd) COSSAP_bde COSSAP_celp COSSAP_chart
21:43:34 (snpslmd) COSSAP_cw_filter_hdl COSSAP_cw_filter_sds COSSAP_dab
21:43:34 (snpslmd) COSSAP_dcg_ad21020 COSSAP_dcg_ansic COSSAP_dcg_ariel32c
21:43:34 (snpslmd) COSSAP_dcg_fe COSSAP_dcg_gc COSSAP_dcg_krc
21:43:34 (snpslmd) COSSAP_dcg_lsic30s COSSAP_dcg_m96000 COSSAP_dcg_mp
21:43:34 (snpslmd) COSSAP_ddk_arm COSSAP_ddk_devlp COSSAP_ddk_dsp1610
21:43:34 (snpslmd) COSSAP_ddk_hawk COSSAP_ddk_nec COSSAP_ddk_oak
21:43:34 (snpslmd) COSSAP_ddk_pine COSSAP_ddk_ssp16xx COSSAP_ddk_tic5x
21:43:34 (snpslmd) COSSAP_ddk_tic5xx COSSAP_dect COSSAP_dvb
21:43:34 (snpslmd) COSSAP_ecc COSSAP_gsmdve COSSAP_gsmdve_utils
21:43:34 (snpslmd) COSSAP_gsmefrsc COSSAP_gsmeq COSSAP_gsmfrcc
21:43:34 (snpslmd) COSSAP_gsmfrsc COSSAP_gsmhrcc COSSAP_gsmhrsc
21:43:34 (snpslmd) COSSAP_gsmphy COSSAP_is136 COSSAP_is95
21:43:34 (snpslmd) COSSAP_matlab COSSAP_mfd COSSAP_mpeg2
21:43:34 (snpslmd) COSSAP_pdc COSSAP_qed COSSAP_sds
21:43:34 (snpslmd) COSSAP_srcfd COSSAP_vcg_generic COSSAP_vcg_synopsys
21:43:34 (snpslmd) COSSAP_vcg_vantage COSSAP_vdefcg COSSAP_vdefcg_vlgxl
21:43:34 (snpslmd) COSSAP_vsiccg BC-FPGA-VHDL Vivace-Simulator
21:43:34 (snpslmd) Vivace-GUI Vivace-Elaborator Early-Access-Technology
21:43:34 (snpslmd) ECO-Compiler ECO-Compiler CA-Frame
21:43:34 (snpslmd) CA-Utils CA-Foundation CA-CP-Basic
21:43:34 (snpslmd) CA-CP-Standard CA-CP-Advanced CA-Chip-Edit
21:43:34 (snpslmd) CA-Optimization CA-Timer CA-Hier-Timer
21:43:34 (snpslmd) PrimeTime Design-Estimator Design-Estimator-FPI
21:43:34 (snpslmd) VDesktop-Verilog VDesktop-VHDL VDesktop-GUI
21:43:34 (snpslmd) VDesktop-Debug Vivace-HDL-Analyzer Vivace-VHDL-Analyzer
21:43:34 (snpslmd) Vivace-Model-Compiler Vivace-Core Vivace-Debug
21:43:34 (snpslmd) DW-IP-Developer DW-IP-Consultant ARKOS-Rtlcomp
21:43:34 (snpslmd) ARKOS-Scomp ARKOS-Mcomp ARKOS-Simul
21:43:34 (snpslmd) ARKOS-Ice ARKOS-A ARKOS-B
21:43:34 (snpslmd) ARKOS-C ARKOS-D ARKOS-E
21:43:34 (snpslmd) VDesktop-VCDTrans Vivace-Pro Vivace-Expert
21:43:34 (snpslmd) Vivace-Express Verification-Token Cyclone-Code-Generator
21:43:34 (snpslmd) Vivace-Code-Generator Mixed-Language Mixed-Paradigm
21:43:34 (snpslmd) Test-IEEE-Std-1149-1 HighLevel-Power-Analysis HighLevel-Power-Optimization
21:43:34 (snpslmd) DesignWare-MGI DesignWare-Developer-MGI BC-Schedule
21:43:34 (snpslmd) Behavioral-Analyzer DesignWare-Foundation-Expert RTL-Analyzer
21:43:34 (snpslmd) RTL-Analyzer-Shell RTL-Analyzer-DAP RTL-Analyzer-Shell-DAP
21:43:34 (snpslmd) Design-Analyzer-DAP Millennium-DRC Millennium-ATPG-STD
21:43:34 (snpslmd) Millennium-FS Millennium-ATPG-EE Millennium-Eval
21:43:34 (snpslmd) Millennium-Beta MC-Pro MCE
21:43:34 (snpslmd) MCE-Eval MCE-Base MCD
21:43:34 (snpslmd) DCM-Delay-Calculation Design-Budgeting DC-Ultra-Features
21:43:34 (snpslmd) DC-Ultra-Opt Protocol-Compiler-Analysis Protocol-Compiler-COutput
21:43:34 (snpslmd) Cyclone-cosim Stamp-Compiler DesignWare-Foundation-Power
21:43:34 (snpslmd) PrimeTime-Plus SNPS-MOTIVE MOTIVE-PrimeTime
21:43:34 (snpslmd) SNPS-CSL MC-Pro-RP SynLib-VHDLSimMdl
21:43:34 (snpslmd) SynLib-VerilogSimMdl FPGA-HDL-Bundle FPGA-VHDL-Bundle
21:43:34 (snpslmd) VSS-Tran VSS-NEC-Tran CD-MSSC-Cross-Probe
21:43:34 (snpslmd) CD-MSSC-Netlist CD-GDII-Link Test-IDDQ
21:43:34 (snpslmd) Test-BIST Test-BSDL Power-Optimization
21:43:34 (snpslmd) DC-Beta HDL-Advisor DesignSource
21:43:34 (snpslmd) DS-Schem-Gen DS-Verinet DS-Vhdlnet
21:43:34 (snpslmd) HDL-Advisor-Shell HDL-Advisor-Shell-Package HDL-Advisor-Package
21:43:34 (snpslmd) DesignSource-Package DS-Schem-Gen-Package DS-Verinet-Package
21:43:34 (snpslmd) DS-Vhdlnet-Package EDIF-Reader EDIF-Netlist-Writer
21:43:34 (snpslmd) EDIF-Schematic-Writer VHDL-Netlist-Writer Verilog-Netlist-Writer
21:43:34 (snpslmd) TDL-Reader TDL-Writer Espresso-Reader
21:43:34 (snpslmd) Espresso-Writer Equation-Reader Equation-Writer
21:43:34 (snpslmd) FSM-Reader FSM-Writer MIF-Reader
21:43:34 (snpslmd) MIF-Writer VHDL-To-BE VHDL-Analyzer
21:43:34 (snpslmd) Parse-Tree-Translator Verilog-To-BE Verilog-Parser
21:43:34 (snpslmd) Cyclone-VHDL-Analyzer Cyclone-HDL-Analyzer Cyclone-Elaborator
21:43:34 (snpslmd) Cyclone-Simulator Cyclone-GUI Protocol-Compiler-UI
21:43:34 (snpslmd) Protocol-Compiler-Synth SGE-Tool Syn-Library-Compiler
21:43:34 (snpslmd) Cyclone-Core HDL-Advisor-Estimator HDL-Advisor-Shell-Estimator
21:43:34 (snpslmd) Estm-HDL-Advisor HDL-Advisor-Estimator-Package HDL-Advisor-Shell-Estm-Package
21:43:34 (snpslmd) DesignSource-Estimator-Package DS-Schem-Gen-Estimator-Package DS-Verinet-Estimator-Package
21:43:34 (snpslmd) DS-Vhdlnet-Estimator-Package Estm-HDL-Advisor-Package EDIF-Netlist-Read-DC
21:43:34 (snpslmd) EDIF-Netlist-Write-DC CD-GDI CD-REX
21:43:34 (snpslmd) TC-Beta ShortCut-DC-Pro ShortCut-DC-Expert
21:43:34 (snpslmd) TBM-Manager-UI TBM-VSS-Check BC-VHDL
21:43:34 (snpslmd) BC-HDL VSS-Backplane DesignWare-Cardbus
21:43:34 (snpslmd) DesignWare-ISA-PnP DesignWare-8051MCU Protocol-Compiler-FML
21:43:34 (snpslmd) Power-Optimization-Upgrade Shortcut-FPGA DesignWare-Foundation
21:43:34 (snpslmd) BC-FPGA-HDL WRITE CTV-Interface
21:43:34 (snpslmd) DC-Cadence-Interface DC-Expert DC-Falcon-Interface
21:43:34 (snpslmd) DC-Layout-Interface DC-SDF-Interface Design-Analyzer
21:43:34 (snpslmd) Design-Compiler Designware-Basic Designware-FPGA-Basic
21:43:34 (snpslmd) DW-Developer DesignWare-FloatingPoint DesignWare-8051
21:43:34 (snpslmd) DesignWare-8051-Source DesignWare-PCI DesignWare-PCI-Source
21:43:34 (snpslmd) ECL-Compiler FPGA-Compiler FPGA-Library-Compiler
21:43:34 (snpslmd) FPGA-Option HDL HDL-Compiler
21:43:34 (snpslmd) Interface-Shell Library-Compiler LSI-Interface
21:43:34 (snpslmd) Mentor-Interface SGE-DC-Interface SGE-EDIF-Interface
21:43:34 (snpslmd) SGE-VHDL-Interface SGE-Verilog-Interface SynLib-ALU
21:43:34 (snpslmd) SynLib-AdvMath SynLib-Eval SynLib-Seq
21:43:34 (snpslmd) Synopsys Synopsys-Queue Synopsys-Release
21:43:34 (snpslmd) TDL-Interface Test-ATPG Test-Custom-Protocols
21:43:34 (snpslmd) Test-Compiler Test-Compiler-Remodel Test-Compiler-Plus
21:43:34 (snpslmd) DesignTime VHDL-Compiler VSS-Analyzer
21:43:34 (snpslmd) VSS-CLI VSS-Cadence-Interface VSS-Debugger
21:43:34 (snpslmd) VSS-Falcon-Interface VSS-LAI-Models VSS-LMSI
21:43:34 (snpslmd) VSS-Lib-Tools VSS-SDF-Interface VSS-SGE-Tool
21:43:34 (snpslmd) VSS-Simulator VSS-Utilities VSS-Wave-Display
21:43:34 (snpslmd) VSS-XP-Accelerator VSS-VIP-Interface VSS-GateSim
21:43:34 (snpslmd) VSS-CompiledSim VSS-SPC VSS-Verilog-PLI
21:43:34 (snpslmd) Floorplan-Management SNPS-Keygen SynLib-FltTol
21:43:34 (snpslmd) SynLib-Control TestSim TestManager
21:43:34 (snpslmd) Leakage-Power Power-Analysis VSS-Model-Developer
21:43:34 (snpslmd) CD-Model-Developer CD-Compiled-Sys-Gen CD-Compiled-Lib-Gen
21:43:34 (snpslmd) CD-Present-Layer-Gen CD-Present-Builder CD-Vhdlgen-Gen
21:43:34 (snpslmd) CD-Vhdlgen-GUI Behavioral-Compiler VSS-SmartModels
21:43:34 (snpslmd) DC-Min-Area-Retime DesignWare-PCIbasic SynLib-PCIbasic
21:43:34 (snpslmd) SynLib-DSPFIR RMAN_RUN VT_VCS_NTBE
21:43:34 (snpslmd) XVVCDebugger VCSCompiler VCSRuntime
21:43:34 (snpslmd) VCSRuntimeLimited VCSNativeCode VCSiCompiler
21:43:34 (snpslmd) VCSiRuntime VCSiRuntimeLimited VCSParallelCompiler
21:43:34 (snpslmd) VCSParallelRuntime VCSParallelThread VMCCompiler
21:43:34 (snpslmd) VMCRuntime VMCEvaluation VCSTools
21:43:34 (snpslmd) VCSlm_Hm LMCSwift VCSPostProcDebugger
21:43:34 (snpslmd) VMCGeneratorUnlocked VMCExpress_Compiler VCSAMSCompiler
21:43:34 (snpslmd) VCSAMSRuntime VT_UnifiedCoverage VT_64Bit
21:43:34 (snpslmd) VT_OtherTechnology VT_CoverageURG VT_NativeTBDebuggerGui
21:43:34 (snpslmd) VT_NTB VT_CBUG VT_Visual
21:43:34 (snpslmd) VT_SVAssertionCompiler VT_SDebug VT_Coverage
21:43:34 (snpslmd) VT_DVENTB VT_Pioneer VT_AssertionIP
21:43:34 (snpslmd) VT_SYSTEMC21 VT_AssertionsRuntime VT_CoverageRuntime
21:43:34 (snpslmd) VT_LCA_Coverage VT_LCA_DEBUG VT_LCA_Assertions
21:43:34 (snpslmd) VT_LCA_Language VT_LCA_MixedSignal vera_rtime
21:43:34 (snpslmd) VT_DVE_COV VT_VCS_BETA_Features VT_VCS_LCA_Features
21:43:34 (snpslmd) VT_VCS_Advanced_Features VT_VCS_BETA_Program VT_PVCSCompiler_Net
21:43:34 (snpslmd) VCSOldPostProcDebugger_Node FusionVantageLmcInterface VCSCompile
21:43:34 (snpslmd) VCSiCompile VCSOldPostProcDebugger_Net vsecP_OEM_VCS_FUJITSU_GEN_NL
21:43:34 (snpslmd) vsecP_OEM_VCS_FUJITSU_RUN_NL vsecP_OEM_VCS_FUJITSU_USE_NL vsecP_OEM_VCS_FUJITSU_GEN_NW
21:43:34 (snpslmd) vsecP_OEM_VCS_FUJITSU_RUN_NW vsecP_OEM_VCS_FUJITSU_USE_NW XVCSiDebugger
21:43:34 (snpslmd) XVCSDebugger VCS-Express-Compile VCS-Express-Runtime
21:43:34 (snpslmd) VCSCompiler_Node VCSRuntime_Node VCSRuntimeLimited_Node
21:43:34 (snpslmd) VCSNativeCode_Node VCSCompiler_Net VCSRuntime_Net
21:43:34 (snpslmd) VCSRuntimeLimited_Net VCSNativeCode_Net VCSiCompiler_Node
21:43:34 (snpslmd) VCSiRuntime_Node VCSiDebugger_Node VCSiRuntimeLimited_Node
21:43:34 (snpslmd) VCSiCompiler_Net VCSiRuntime_Net VCSiDebugger_Net
21:43:34 (snpslmd) VCSiRuntimeLimited_Net VCSDebugger_Node VCSParallelCompiler_Node
21:43:34 (snpslmd) VCSParallelRuntime_Node VCSParallelThread_Node VCSTools_Node
21:43:34 (snpslmd) VCSlm_Hm_Node VCSPostProcDebugger_Node VCSDebugger_Net
21:43:34 (snpslmd) VCSParallelCompiler_Net VCSParallelRuntime_Net VCSParallelThread_Net
21:43:34 (snpslmd) VCSTools_Net VCSTools_Net VCSlm_Hm_Net
21:43:34 (snpslmd) VCSPostProcDebugger_Net VMCCompiler_Node VMCRuntime_Node
21:43:34 (snpslmd) VMCEvaluation_Node VMCGeneratorUnlocked_Node VMCExpress_Compiler_Node
21:43:34 (snpslmd) VMCCompiler_Net VMCRuntime_Net VMCEvaluation_Net
21:43:34 (snpslmd) VMCGeneratorUnlocked_Net VMCExpress_Compiler_Net LMCSwift_Node
21:43:34 (snpslmd) LMCSwift_Net CoverMeter CoverMeterOBC
21:43:34 (snpslmd) VCSAMSCompiler_Net VCSAMSRuntime_Net VT_Assertions
21:43:34 (snpslmd) SNPS-Assertions VT_Testbench VT_SystemVerilog
21:43:34 (snpslmd) VCSMXRunTime_Net VCSMXiRunTime_Net Magellan-Sim
21:43:34 (snpslmd) VT_SVDesign VT_SVAssertions VT_SVTestbench
21:43:34 (snpslmd) VT_NativeTestbench VT_DVE VT_UCLI
21:43:34 (snpslmd) VT_TestbenchRuntime VT_LCA_Testbench PVCSCompiler_Net
21:43:34 (snpslmd) PVCSRuntime_Net VT_VCS_Power_Management VT_VCS_Checker
21:43:34 (snpslmd) VT_VCS_Echo VHDL-Tools CmMonitor
21:43:34 (snpslmd) hspice hspice_cosim hspice_adv
21:43:34 (snpslmd) hspicewin encrypt metaencrypt3des
21:43:34 (snpslmd) hspiceva hspicerf COSMOS_SCOPE
21:43:34 (snpslmd) COSMOS_GUIDE CXp_GUI CXp_Analysis
21:43:34 (snpslmd) CXp_CircuitEnvironment him_mod him_mm_pi
21:43:34 (snpslmd) him_mb
21:43:34 (snpslmd)
21:43:34 (snpslmd) Licenses are case sensitive for TE_CATS
21:43:34 (snpslmd)
21:43:34 (snpslmd) EXTERNAL FILTERS are OFF
21:43:34 (lmgrd) snpslmd using TCP-port 41799
21:43:34 (snpslmd) Serving features for the following vendor names:
snpslmd CADABRA EPIC ISE-TCADd TE_CATS adalmd anagram archprod avantd chrysalisd everest hscd innologd la_dmon leda metasoftd nassd numeritchd saber_dmn sandwork sigmacd slat snpsOEM1 snpsOEM2 snpsOEM3 snpsOEM4 snpsOEM5 snpsOEM6 snpsOEM7 snpsOEM8 snpsOEM9 ssilmd synopsysd tmald vcsd
21:43:36 (snpslmd) ------------------------------------------------------------------
21:43:36 (snpslmd) Checking the integrity of the license file....
21:43:36 (snpslmd) Valid SSS feature found.
21:43:36 (snpslmd) The feature is needed to enable the other keys in your license file.
21:43:36 (snpslmd) ------------------------------------------------------------- |
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发表于 2011-7-31 12:37:08
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