CMOS Current-Mode Circuits for Data Communications

asic_ant

Dedication v
Preface xiii
Acknowledgments xvii
1. VOLTAGE-MODE VERSUS CURRENT-MODE : A CRITICAL
COMPARISON 1
1.1 Ideal Current-Mode Circuits 2
1.2 Topology Duality of Current-Mode Circuits 4
1.3 Characteristics of Current-Mode Circuits 6
1.3.1 Input and Output Impedances 6
1.3.2 Bandwidth 6
1.3.3 Slew Rate 7
1.3.4 Propagation Delay 9
1.3.5 Supply Voltage Sensitivity 9
1.3.6 ESD 11
1.4 Summary 12
2. DESIGN TECHNIQUES FOR CURRENT-MODE CIRCUITS 13
2.1 Basic Current Amplifiers 13
2.2 Output Impedance Boosting Techniques 15
2.2.1 Basic Cascodes 15
2.2.2 Regulated and Multi-Regulated Cascodes 17
2.2.3 Pseudo-Cascodes 18
2.2.4 Low-Voltage Cascodes 19
2.3 Input-Impedance Reduction Techniques 20
2.3.1 Input-Capacitance Reduction 20
2.3.2 Active Feedback 21
2.3.3 Bootstrapping 21
2.4 Mismatch Compensation Techniques 22
2.5 Power Reduction Techniques 25
2.6 Bandwidth Enhancement Techniques 26
2.6.1 Resistor Series Peaking 27
2.6.2 Inductor Series Peaking 28
2.6.3 Current Feedback 31
2.7 Dynamic Range Improvement Techniques 32
2.8 Active Inductors 34
2.8.1 Topologies of Active Inductors 35
2.8.2 Noise of Active Inductors 43
2.8.3 Dynamic Range 47
2.9 Summary 47
3. WIRE CHANNELS 49
3.1 Resistances 50
3.2 Capacitances 54
3.3 Inductances 55
3.4 ModeHng of Wire Channels 59
3.4.1 Lumped RC Model 59
3.4.2 Distributed RC Model 60
3.4.3 Elmore Model 61
3.4.4 Transmission-Line Model 62
3.5 Transmission Line Effects 66
3.6 Termination Schemes 71
3.6.1 Series Termination 72
3.6.2 Parallel Termination 74
3.6.3 Parallel AC Termination 74
3.6.4 Thevenin Termination 75
3.7 Broadband Impedance Matching Networks 75
3.7.1 Passive Impedance Matching 75
3.7.2 Active Impedance Matching 75
3.8 Summary 79
4. ELECTRICAL SIGNALING
FOR HIGH-SPEED DATA LINKS 81
4.1 Voltage-Mode Signaling versus Current-Mode Signaling -
A Comparison 81
4.2 Voltage-Mode Signaling 84
4.2.1 Single-Ended Signaling 84
4.2.2 Fully Differential Signaling 85
4.2.3 Pseudo-Differential Signaling 86
4.2.4 Voltage-Mode Incremental Signaling 87
4.3 Current-Mode Signaling 89
4.3.1 Unipolar Current-Mode Signaling 89
4.3.2 Bipolar Current-Mode Signaling 90
4.3.3 Current-Mode Incremental Signaling 91
4.4 Summary 92
5. CURRENT-MODE TRANSMITTERS 95
5.1 Introduction 95
5.2 Serialization 98
5.2.1 Transmission-Gate Multiplexers 100
5.2.2 Pseudo-nMOS Multiplexers 101
5.2.3 Current-Steering Multiplexers 102
5.2.4 Lee's Multiplexer 102
5.2.5 Yang's Multiplexer 103
5.2.6 Current-Mode Multiplexers 104
5.3 Drivers 106
5.3.1 Inverter Drivers 107
5.3.2 Open-Drain Drivers 107
5.3.3 Low-Voltage Differential-Signaling Drivers 109
5.3.4 Class A Current-Mode Drivers 109
5.3.5 Class AB Current-Mode Drivers 111
5.4 Pre-Emphasis 113
5.4.1 Voltage-Mode Pre-Emphasis 114
5.4.2 Current-Mode Pre-Emphasis 114
5.4.3 Current-Mode Power-Area Efficient Pre-Emphasis 115
5.4.4 Current-Mode Direct Pre-Emphasis 121
5.5 Serial Link Transmitters 122
5.5.1 ADC-Based Transmitter 123
5.5.2 Current-Mode Class A 2PAM Transmitter 124
5.5.3 Current-Mode Class AB 2PAM Transmitter 124
5.5.4 Current-Mode Power-Insensitive Class AB 2PAM
Transmitter 126
5.5.5 Current-Mode Area-Power Efficient 4PAM Transmitter
5.5.6 Current-Mode Direct Pre-Emphasis 4PAM Transmitters
133
5.6 Summary 134
6. CURRENT-MODE RECEIVERS 137
6.1 Current-Mode Pre-Amplifiers 138
6.2 Clock and Data Recovery Using Phase-Picking 140
6.2.1 Samplers 143
6.2.2 2x-0versampling Clock and Data Recovery 148
6.2.3 3x-Over sampling Clock and Data Recovery 150
6.2.4 4x-0versampling Clock and Data Recovery 152
6.3 Clock and Data Recovery Using Phase-Tracking 154
6.3.1 Phase-Frequency Detectors 155
6.3.2 Charge Pumps 172
6.3.3 Voltage-Controlled Ring Oscillators 181
6.3.4 Current-Controlled Ring Oscillators 189
6.3.5 Current-Mode Phase-Locked Loops 191
6.4 Data Recovery Using Current Integration 195
6.4.1 Voltage-Mode Integrating Receivers 196
6.4.2 Current-Mode Integrating Receivers 200
6.5 Noise Characteristics of Phase-Locked Loops 204
6.5.1 Phase Noise of Oscillators 204
6.5.2 Phase Noise of Phase-Locked Loops 209
6.6 Summary 213
7. SWITCHING NOISE AND GROUNDING OF MIXEDMODE
CIRCUITS 215
7.1 Introduction 215
7.2 Effects of Switching Noise 218
7.2.1 On-Chip Supply Voltage Fluctuation and Ground
Bouncing 218
7.2.2 Noise Margin Reduction 218
7.2.3 DC Operation Point of Analog Circuits 218
7.3 Analysis of Switching Noise 220
7.3.1 Triangle Waveform Approach 221
7.3.2 a-Power Law Approach 222
7.3.3 Improved a-Power Law Approach 225
7.3.4 Partial Buff'er Switching Approach 227
7.3.5 Peak Switching Noise Approach 229
7.3.6 Application Specific Device Modeling Approach 231
7.4 Switching Noise Reduction Techniques 232
7.4.1 Multiple Bonding Pads and Pins 233
7.4.2 Pre-Skewing 233
7.4.3 Decoupling Capacitors 234
7.4.4 Balanced Drivers 236
7.4.5 Current-Mode Logic Circuits 236
7.5 Grounding in Mixed-Mode Circuits 236
7.5.1 Substrate Modeling 237
7.5.2 Analog and Digital Grounding 238
7.5.3 Substrate Grounding 239
7.5.4 Passive Guard Rings 239
7.5.5 Active Guard Rings 241
7.6 Summary 241
8. ESD PROTECTION 243
8.1 ESD Sources 244
8.1.1 Human-Body Model 244
8.1.2 Machine Model 245
8.1.3 Charged Device Model 245
8.2 ESD Protection Principles 246
8.2.1 Current Limiting of n-Well Resistors 247
8.2.2 Avalanche Multiplication of nMOS Transistors 248
8.3 ESD Protection Devices 249
8.3.1 n-Well Resistors 250
8.3.2 Diodes 250
8.3.3 Gate-Grounded nMOS Transistors 251
8.3.4 Gate-Coupled nMOS transistors 253
8.3.5 Silicon-Controlled Rectifiers 254
8.4 ESD Protection Circuits 256
8.4.1 Basic ESD Protection Circuits 257
8.4.2 Challenges in ESD Protection 257
8.4.3 Polysilicon Diodes 259
8.4.4 Distributed ESD Protection Circuits 260
8.4.5 ESD Protection with Negative Capacitors 262
8.4.6 Poly Back-End Ballast with Segmentation 263
8.4.7 Soft-Grounded-Gate nMOS MET 264
8.4.8 Domino nMOS MET 265
8.5 Chapter Summary 266
References 269
Index 287

asic_ant

继续………………

jianchongzhou

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zhanweisu27

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zhanweisu27

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zhanweisu27

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semitao

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apple_fandai

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apple_fandai

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