DAC的问题

domino.kk · 发表于 2011-1-13 13:44:22

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我现在做了一个10位电流舵DA，输出5uA-5mA电流，想在输出经过镜像变换得到5nA-5uA电流，有谁知道如何实现，还望指教

fhchen2002 · 发表于 2011-1-13 18:58:36

建议你打消這個念頭
The reason is the following:

Unit current source 5 uA, mismatch OK (in case you know how to determine the W/L, VGS, etc.) according the mismtach characterizataion report provided by the foundry, and you know how to rung Monte Carlo simulations to verify your design.

Now you change the unit current source from 5 uA to 5 nA.
The mismatch between your current sources (DAC elements) will be deteriorated a lot. (厳重惡化)
(Matching gets worse with smaller bias current).
The INL and DNL of your DAC will become very bad.

If your superviser or teacher asked you to add this option, you may want to convince him that this might not sound like a good idea. The reason is described above.

hezudao · 发表于 2011-1-14 05:53:20

开玩笑？

domino.kk · 发表于 2011-1-14 13:49:29

回复 2# fhchen2002

那我要做个5nA-5uA的DA怎么办呢

fhchen2002 · 发表于 2011-1-14 14:26:11

回复 4# domino.kk

Clarification

Unit current source: 5 nA
Maximum current output: 1023 * 5 nA
Is this part of your design specification?

fhchen2002 · 发表于 2011-1-14 15:01:17

Can you specify your power supply level (typical and minimum)
The resistive load (on-chip or off-chip) value
Single-ended output or fully differential output ...

fhchen2002 · 发表于 2011-1-14 15:26:21

本帖最后由 fhchen2002 于 2011-1-18 06:38 编辑

回复 4# domino.kk

1. Do not use wide width device.  (for instance,
W_min = 0.24 um,
Width with single contact = 0.42 um,
Width with two contacts is 0.89 um.
Choose width = 0.89 um, and no more wider. <- Choose a MOS device, without significant narrow-width effect, but narrow enough.

2. Choose as long channel length as possible.

3. If possible, use pMOS as the unit-current mirror device, instead nMOS.
The reason is the mobility of pMOS is smaller.  With the same bias current, the (VGS - VT) can be effectively larger.

Steps 1-3 are enforced to make maximum VGS - VT possible.

4. Determine Large enough VGS - VT.

5. Employ cascode to increase the output impedance of each unit current mirror.
Example:
Single ended output
Full-scale current output: 1023 * 5 nA ~= 5 uA
R_load = 200 KOhm (full-scale: ~= 5 uA * 200 KOhm ~= 1.0 V)
When all current sources are in parallel, you see r_out / 1,023 of the 1023 unit-current sources.
Make sure this number is much greater than 200 KOhm.
This means your unit-current source needs to have r_out >> 200 MOhm

6. Separate your current mirror units from the decoder circuits. Put all your current mirrors together and make 2-D scramble.  This is to minimize the impact of process-dependent gradient.

7. Put at least two columns of dummy current mirrors at the array edge (both sides) to minimize microloadings.
8. Depending on DNL and INL design specification, determine binary weigthted current mirror and thermometer coded current mirror.

寫得比實做容易

domino.kk · 发表于 2011-1-21 15:36:24

回复 7# fhchen2002

你好，谢谢你的细心解答，我一开始是这样做的，电源电压5V，用的是0.35um工艺，单位电流源的尺寸选择w=450nm,l=23.5um。这样可以保证一定的Vgs-Vth，不过我不知道一般要保证多大的Vgs-Vth，还有一个问题我不知道是不是开关电路部分出问题了还是怎么的，输出电路最后有很大的尖脉冲，尖脉冲全部出现在转换过程中。详细的我有仿真图，希望能留下你的邮箱地址，我发邮件给你看也可以

domino.kk · 发表于 2011-1-21 16:03:02

回复 7# fhchen2002

还有一个问题，我实际测试时要用到100K的电阻，还有我做的是差分的双端输出，但实际给下级电路是单端的如何实现呢

fuyibin · 发表于 2011-1-21 20:56:37

回复 fhchen2002

你好，谢谢你的细心解答，我一开始是这样做的，电源电压5V，用的是0.35um工艺， ...
domino.kk 发表于 2011-1-21 15:36

登录/注册后可看大图

看看你运气好不好吧,反正感觉是个很悬乎的东西,5nA，漏电?
什么地方用，需要这么小的功耗啊，
100K load resistor，这个...，noise要多大啊
你的速度要求是什么？
整个方案评估过没有？
在学校里自己瞎整整还可以，反正是烧国家钱

[求助] DAC的问题

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