verilog FPGA 中状态转换程序中出现的问题

zhengguo22 · 发表于 2010-11-6 20:00:29

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module contral(clk1hz,rst_n,hold,
led,num,flash);
input clk1hz;
input rst_n;
input hold;  //incident happen
//input INTI;  //红绿灯初始状态
output [2:0] led; //红绿灯
output [4:0] num; //显示的倒计时
output flash; //闪烁的标识符
parameter INTI = 3'b100;
reg [2:0] state;  // 当前状态
reg [4:0] num_r; //显示的倒计时
reg flash_r;
always @ (posedge clk1hz or negedge rst_n)
if(!rst_n)
begin
  num_r <= 5'b0;
end
else if(hold)
begin
  state <= 3'b100;
  flash_r <= 1'b1;
end
else
begin
  num_r <= num_r + 1'b1;
end

always @ (posedge clk1hz or negedge rst_n)
if(!rst_n)
state <= INTI;
else
case(state)
  3'b100:if(num_r == 0)
begin
   num_r <= 5'd5;
   state <= 3'b010;
end
  3'b010:if(num_r == 0)
begin
   num_r <= 5'd20;
   state <= 3'b001;
end
  3'b001:if(num_r == 0)
begin
   num_r <= 5'd25;
   state <= 3'b100;
end
  endcase
assign flash = flash_r;
assign num = num_r;
assign led = state;

endmodule

错误提示：can't resolve multiple constant drivers for net "state.001"
...............
can't resolve multiple constant drivers for net "num_r[4]"
................

等等，错误指示都在红色标注的地方。
不知道问题所在，
请各位高手指教~