一本学习高速D/A转换的好书 WIDE-BANDWIDTH HIGH DYNAMIC RANGE D/A CONVERTERS

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WIDE-BANDWIDTH HIGH
DYNAMIC RANGE D/A
CONVERTERS
by
Konstantinos Doris
Philips Research Laboratories,
Eindhoven, The Netherlands
Arthur van Roermund
Eindhoven University of Technology,
Eindhoven, The Netherlands
and
Domine Leenaerts
Philips Research Laboratories,
Eindhoven, The Netherlands

Published by Springer,
P.O. Box 17, 3300 AA Dordrecht, The Netherlands.

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© 2006 Springer
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Printed in the Netherlands.

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Contents
3 Current Steering DACs 25
3.1 Basic circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.1 Partitioning and segmentation . . . . . . . . . . . . . . . . . . . 26
3.1.2 Current switching network and current sources . . . . . . . . . . 29
3.1.3 Clock-data synchronization circuit . . . . . . . . . . . . . . . . . 29
3.1.4 Auxiliary circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2 Implementations and technology impact . . . . . . . . . . . . . . . . . . 30
4 Dynamic limitations of Current Steering DACs 35
4.1 State of the art in dynamic linearity . . . . . . . . . . . . . . . . . . . . . 35
4.2 Dynamic limitations of current steering DACs . . . . . . . . . . . . . . . 40
4.2.1 Matching and relative amplitude precision . . . . . . . . . . . . . 41
4.2.2 Matching and relative timing precision . . . . . . . . . . . . . . 42
4.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5 Current Steering DAC circuit error analysis 45
5.1 Amplitude domain errors . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.1.1 Relative amplitude inaccuracies . . . . . . . . . . . . . . . . . . 45
5.1.2 Output resistance modulation . . . . . . . . . . . . . . . . . . . 47
5.2 Time domain errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.2.1 Nonlinear settling and output impedance modulation . . . . . . . 48
5.2.2 Asymmetrical switching . . . . . . . . . . . . . . . . . . . . . . 51
5.2.3 Modulation of switching behavior . . . . . . . . . . . . . . . . . 53
5.2.4 Charge feedthrough and injection . . . . . . . . . . . . . . . . . 54
5.2.5 Relative timing inaccuracies . . . . . . . . . . . . . . . . . . . . 56
5.2.6 Power supply bounce and substrate noise . . . . . . . . . . . . . 59
5.2.7 Clock (timing) jitter . . . . . . . . . . . . . . . . . . . . . . . . 63
5.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6 High-level modeling of Current Steering DACs 67
6.1 System modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.1.1 System layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.1.2 System excitations and responses . . . . . . . . . . . . . . . . . 69
6.1.3 System parameters . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.1.4 Subsystem interaction . . . . . . . . . . . . . . . . . . . . . . . 71
6.1.5 System modulation . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.2 Error properties and classification . . . . . . . . . . . . . . . . . . . . . 72
6.2.1 Error properties . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.2.2 Error classification . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.3 Functional error generation mechanisms . . . . . . . . . . . . . . . . . . 79
6.3.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.2 Algorithmic modeling . . . . . . . . . . . . . . . . . . . . . . . 80
6.3.3 Functional modeling . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.4 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
vi
Contents
6.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
7 Functional modeling of timing errors 89
7.1 Non-uniform timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7.1.1 The Equivalent Timing error of a transition . . . . . . . . . . . . 89
7.1.2 Non-uniform timing in the process of signal sampling . . . . . . 91
7.1.3 Non-uniform timing in the process of signal creation . . . . . . . 92
7.2 Stochastic non-uniform timing analysis . . . . . . . . . . . . . . . . . . 95
7.2.1 Correlated non-uniform timing . . . . . . . . . . . . . . . . . . . 95
7.2.2 White non-uniform timing . . . . . . . . . . . . . . . . . . . . . 97
7.2.3 RZ and NRZ waveforms . . . . . . . . . . . . . . . . . . . . . . 100
7.3 Deterministic non-uniform timing . . . . . . . . . . . . . . . . . . . . . 103
7.3.1 Non-linear mapping of time domains . . . . . . . . . . . . . . . 103
7.3.2 Non-uniform timing in signal creation . . . . . . . . . . . . . . . 105
7.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
8 Functional analysis of local timing errors 109
8.1 Local timing error analysis . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.1.1 Equivalent timing error calculation . . . . . . . . . . . . . . . . . 109
8.1.2 Signal error calculation . . . . . . . . . . . . . . . . . . . . . . . 113
8.2 High level architectural parameter tradeoffs: segmentation . . . . . . . . 116
8.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9 Circuit analysis of local timing errors 119
9.1 Circuit analysis with linear models . . . . . . . . . . . . . . . . . . . . . 119
9.1.1 Circuit behavioral-level analysis of timing errors in a chain . . . . 120
9.1.2 Transistor level analysis . . . . . . . . . . . . . . . . . . . . . . 126
9.2 Local timing error tradeoffs . . . . . . . . . . . . . . . . . . . . . . . . . 135
9.2.1 Switch timing errors . . . . . . . . . . . . . . . . . . . . . . . . 135
9.2.2 Latch timing errors . . . . . . . . . . . . . . . . . . . . . . . . . 137
9.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
10 Synthesis concepts for CS DACs 139
10.1 Information management in the CS DAC . . . . . . . . . . . . . . . . . . 139
10.1.1 The basic current steering DAC hardware . . . . . . . . . . . . . 141
10.1.2 Information sources . . . . . . . . . . . . . . . . . . . . . . . . 141
10.1.3 Optional hardware: detection and control operations . . . . . . . 142
10.1.4 Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
10.1.5 Space/Time error mapping and processing . . . . . . . . . . . . . 145
10.2 Synthesis Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
10.3 A-posteriori error correction methods . . . . . . . . . . . . . . . . . . . 148
10.3.1 Calibration in amplitude and time domain . . . . . . . . . . . . . 148
10.3.2 Generalized mapping . . . . . . . . . . . . . . . . . . . . . . . . 151
10.3.3 Applications of generalized mapping . . . . . . . . . . . . . . . 155
vii
Contents
10.3.4 Realization issues of the generalized mapping concept . . . . . . 156
10.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
11 Design of a 12 bit 500 Msample/s DAC 159
11.1 Design approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
11.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.2.1 Signaling and circuit logic . . . . . . . . . . . . . . . . . . . . . 160
11.2.2 Power supply and biasing . . . . . . . . . . . . . . . . . . . . . 161
11.2.3 Thermometer/binary bits partitioning . . . . . . . . . . . . . . . 162
11.3 Switched-Current cell .
11.3.1 Current source
11.3.2 Switch
11.4 Decoder, data synchronization and conditioning . . . . . . . . . . . . . . 174
11.4.1
11.4.2 Delay equalization . . .
11.4.3 Master-slave latches and drivers
11.4.4 Clock buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
11.5 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
11.6 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
11.6.1 DC linearity measurements . . . . . . . . . . . . . . . . . . . . . 180
11.6.2 AC linearity measurements . . . . . . . . . . . . . . . . . . . . . 181
11.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
References 185
A Output spectrum for timing errors 199
A.1 Power spectrum of y(t) for random timing errors . . . . . . . . . . . . . 199
A.2 Spectrum of y(t) for deterministic timing errors . . . . . . . . . . . . . . 202
B Literature data 203

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登录/注册后可看大图 Wide-Bandwidth High Dynamic Range D/A ConvertersSeries: The Springer International Series in Engineering and Computer Science , Vol. 871 Doris, Konstantinos, Roermund, Arthur H. M.van, Leenaerts, Domine 2006, XVII, 204 p., Hardcover ISBN: 978-0-387-30415-1 This item usually ships in 2-3 days. $129.00                                 登录/注册后可看大图

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About this book
Wide-bandwidth high dynamic range Digital to Analog Converters (D/A) are essential elements of modern systems, e.g. multi-carrier communication systems. Current Steering D/A converters offer the potential to achieve high dynamic range for wide frequency bandwidths, however, their performance at higher frequencies is usually limited by strong nonlinear behavior. This behavior is not well understood and impedes performance progress.
Wide-Bandwidth High Dynamic Range D/A Converters presents a structured description of the operation principles and the nonlinear behavior of Current Steering D/A Converters, and shows ways to deal with it in the design phase.
The book provides the reader a thorough understanding of error mechanisms at high frequencies. It explains their effects and shows their dependencies with parameters of the processed signal, the architecture, its circuit blocks and their implementations. A highlight of the book is the detailed treatment of timing errors caused by circuit imperfections due to process mismatch and clock interconnects.
The book follows a unique approach, building an analysis and synthesis framework of concepts with a generic scope beyond the current steering architecture.
The concepts are tested in practice with the design and measurements of a high performance 12b 500MSample/sec Current Steering Digital to Analog Converter realized in 0.18m m CMOS.

Written for:
Engineers and researchers of Mixed-signal and RF circuit design, graduate and under graduate electrical/electronic engineering students, for those interested on specialized topics of high speed Digital to Analog Converters and their current steering implementations.

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