|
|
马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
x
提供一份比较完整的数字电路开发库，包括Standard单元库和IO单元库。
---------------------
目录如下：
IO：
Floorplan： 用于布局用的blackbox形式verilog描述
LEF： SOC Encounter布局布线用苦
Symbol：
Cadence： Cadence符号图
edif： Edif符号图
synopsys： Synopsys符号图
Synopsys： Synopsys用的综合库
TLF： 时序延迟文件
Verilog： 仿真用Verilog描述
STD：
Fastscan： 用于Mentor的DFT工具Fastscan使用的ATPG库
Floorplan： 用于布局用的blackbox形式verilog描述
LEF： SOC Encounter布局布线用苦
Symbol：
Cadence： Cadence符号图
edif： Edif符号图
synopsys： Synopsys符号图
Synopsys： Synopsys用的综合库
TLF： 时序延迟文件
Verilog： 仿真用Verilog描述
----------------
其中ApplicationNotes_DesignKit.txt文件如下：
VeriSilicon SMIC 0.18um High-Density Standared Cell Library Application Notes
1.Recommend Operating Conditions
typ max min
core DC supply voltage(volt) 1.8v 1.98v 1.62v
IO DC supply voltage(volt) 3.3v 3.6v 3.0v
Junction temperature(centigrade) 25 125 0
2.Derating Factors
The derating factors of VeriSilicon SMIC 0.18um High-Density Standared Cell Library given
in document SMIC18STDLib.pdf are for pre-layout estimation only.
3.Synopsys Model
a.The wire load models given in our synopsys library are for your REFERENCE ONLY. So please
create a customized wire load model appropriate for your design.
b.Please consider for which cell, if any, should be added dont_use and dont_touch during
synthesis and ignore our settings.
c.Since our synthesis tools' version may be different from yours, it is recommended that you
create the db file using your own library compiler tools.
d.When reading in the model, synopsys tools will give some warning which should be ignored. The following is the warning list to be ignored:
Warning: Line xxx, The 'values' attribute has a '-x.xxxxxx' value,
which is less than '0.000000' the minimum recommended value of this attribute. (LBDB-272)
Warning: Line xxx, The 'SN' pin of the 'XXXX' design is not a clock pin
and should not be used in the 'related_pin' of 'setup' timing arc. (LIBG-104)
Warning: Line xx, The 'Z' Pin/bus on the 'HOLDHD' cell has no 'function' a
ttribute.
The cell becomes a black box. (LIBG-16)
Information: Line 197792, No internal_power information for the 'TIEHHD' cell. (LBDB-301)
Information: Line 197792, No internal_power information for the 'TIELHD' cell. (LBDB-301)
Warning: Line xx, The 'default_leakage_power_density' attribute is not spe
cified. Using 0.00. (LBDB-172)
Warning: Line 4, The units of time, capacitance, voltage and current are not consistent.(LBDB-602)
4.Ambit Sdf Writing
When using Ambit to write 2.1 version sdf, please use this option
"-edges edged". The following is the eample:
ac_shell> write_sdf -version 2.1 -interconn all -edges edged -splitsethold design.sdf
5.SDF file
If you generate version 2.1 sdf file using synopsys design compiler(Version 2002.08 or
later) or Ambit, please use the script Modify_SDF_2_1.pl to modify
the sdf file before doing back-annotation using Verilog-XL.
file : Synopsys/Modify_SDF_2_1.pl
cmd line : Modify_SDF_2_1.pl sdf_file
result : sdf_file - can be used for back-annotation
sdf_file.bak - back-up file
6.Formality comment
If your design can not pass Synopsys Formality tool, commenting the cell HOLDHD from your design may help you.
7. Cell list comment
There are 499 basic cells in the library and add 9 FILLERC*HD cells in fastscan model.
8. SDF back-annotation simulation
When doing sdf back-annotation in VCS(V6.2 and above), the option "+overlap" is necessary and the following
warning may appears.
Warning : The sum of a negative timing check limits should be greater than or equal to 0. Setting negative
limits to 0. ("<verilog_model_filename>", xxxx). |
|
/2 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2010-9-1 20:48:49
楼主
