使用"vera -proj filename.proj"后产生.v文件,然后使用"VCS *.v"命令,提示
"Error-[UST] Undefined system task
Undefined System Task call to '$vmc_init' "
类似的错,有函数的,有任务的。
找了下该类任务和函数在vera安装文件夹下的lib以及lib下的vlog文件夹下vmc_veri_funext.h文件中有定义。
请问该怎么解决这个问题?谢谢
extern int vmc_size();extern int vmc_init();extern int vmc_init_misctf (int data, int reason, int paramvc);extern int vmc_init_check();extern int vmc_setup_start();extern int vmc_setup_misctf();extern int vmc_system_clock();extern int vmc_start_program();extern int vmc_add_variable();extern int vmc_add_variable_array();extern int vmc_add_variable_array_elmt();extern int vmc_add_interface_signal();extern int vmc_signal_change_misctf(int data, int reason, int paramvc);extern int vmc_add_verilog_task();extern int vmc_done_task_misctf(int data, int reason, int paramvc);extern int vmc_add_vera_task();extern int vmc_vera_task_call();extern int vmc_vera_load();extern int vmc_vera_mload();extern int vmc_vera_pload();extern int vmc_vera_debugger();extern int vmc_vera_add_parameter();extern int vmc_get_export_index();
vshell calls the Vera simulator procedure “vmc_init” through the PLI. vmc_init performs the following five major functions:
i) it loads the Vera assembly language program to be executed by the Vera simulator,
ii) it sets up certain nodes of the Verilog model as callback nodes,
iii) it creates a “master” context of level 0 , which we shall also refer to as “context( 0 ),” for the execution of the main Vera language program,
iv) it places context( 0 ) on “the run queue” of the Vera simulator which holds all Vera language contexts waiting to be run and
v) it calls “vera_main,” the main routine of the Vera simulator.
The nodes which vmc_init establishes as callback nodes in step (ii) are typically: i) the Verilog model's Vera system clock, and ii) those clocks specified by Vera language interface statements.