Conformal LEC

yohuang

NEC Conformal Logical Equivalence Check
CHAPTER 1 INTRODUCTION..................................................................................................................12
1.1 Explanation of Formal Verification ............................................................................................. 12
1.1.1 Property check and logic equivalency check..................................................................................... 12
1.1.2 Verification method........................................................................................................................... 13
1.1.3 Correspondence of verification points ............................................................................................... 14
1.1.4 Black box.......................................................................................................................................... 14
1.1.5 Bus holder ........................................................................................................................................ 14
1.1.6 Handling of logical value X ................................................................................................................ 15
1.1.7 Analysis of mismatch point (simulation) ............................................................................................ 15
1.2 Positioning of Formal Verification in Design Flow ................................................................... 16
1.2.1 Positioning of formal verification in design flow ................................................................................. 16
1.2.2 Supported verification levels.............................................................................................................. 17
1.3 Conformal-LEC Execution Flow.................................................................................................. 18
1.4 Operating Environment ............................................................................................................... 19
CHAPTER 2 RESTRICTIONS ..................................................................................................................20
2.1 Circuit Restrictions ...................................................................................................................... 20
2.2 Tool Restrictions .......................................................................................................................... 22
2.3 Library Restrictions..................................................................................................................... 23
2.4 Known Problems .......................................................................................................................... 24
CHAPTER 3 LIBRARY .............................................................................................................................28
3.1 Library Structure .......................................................................................................................... 28
3.2 Cautions When Using a Library .................................................................................................. 30
3.2.1 Priority order..................................................................................................................................... 30
3.2.2 Messages when reading library......................................................................................................... 30
3.3 Creating Library for Compiled Memory...................................................................................... 31
CHAPTER 4 Conformal-LEC EXECUTION PROCEDURE...................................................................33
4.1 Procedure in OPENCAD environment........................................................................................ 33
4.1.1 OPENCAD environment setting ........................................................................................................ 33
4.1.2 Creation of script file (Do file) ............................................................................................................ 34
4.2 Procedure of Conformal-LEC...................................................................................................... 36
4.2.1 Command flow ................................................................................................................................. 36
4.2.2 Script file editing ............................................................................................................................... 41
4.2.3 Execution of Conformal-LEC............................................................................................................. 42
CHAPTER 5 NOTES AND SETTING METHODS FOR VERIFICATION FLOW ...............................43
5.1 (Recommended) Logic Synthesis Method................................................................................. 43
5.1.1 Logic synthesis facilitating verification............................................................................................... 43
5.1.2 Two-stage verification before and after logic synthesis ..................................................................... 44
5.1.3 change_names -log option ................................................................................................................ 44
5.1.4 Bus naming rule ............................................................................................................................... 45
5.1.5 Array of hierarchy pins (VHDL).......................................................................................................... 46
5.1.6 ungroup ............................................................................................................................................ 47
5.1.7 Optimization of hierarchy boundary................................................................................................... 48
5.2 Complex Computing Unit ............................................................................................................ 49
5.3 Instantiated DesignWare ............................................................................................................. 51
5.4 Compiled Memory Bus Wrapper................................................................................................. 51
5.5 Verification of Clock-Gated Circuit............................................................................................. 53
5.6 Verification Before and After DFT Execution............................................................................ 54
5.6.1 TESTACT..........................................................................................................................................55
5.6.2 NEC BSCAN.....................................................................................................................................55
5.6.3 NEC BIST (RAM BIST) ......................................................................................................................55
5.6.4 TESTBUS .........................................................................................................................................56
5.6.5 Scan path tool made by EDA vendor .................................................................................................56
5.6.6 NEC_SCAN2.....................................................................................................................................56
5.6.7 Verification before and after scan rechaining .....................................................................................57
5.6.8 Verification before and after eFuse circuit insertion ...........................................................................57
5.7 Verification of Each Hierarchy.................................................................................................... 58
5.8 Handling of Bus Holder ............................................................................................................... 59
5.9 Combination Loop Check............................................................................................................ 61
5.10 Verification Before and After Retiming.................................................................................... 62
5.11 Formal Verification Following ECO.......................................................................................... 63
CHAPTER 6 EXAMPLE OF EXECUTION OF Conformal-LEC..........................................................64
6.1 Example of Execution of Combination Circuit.......................................................................... 64
6.2 Example of Verification Before and After Scan Path Circuit Insertion................................... 68
APPENDIX A EXPLANATION OF OPC_LEC .......................................................................................73
A.1 Method of execution.................................................................................................................... 73
A.2 OPC_LEC Interface...................................................................................................................... 74
A.2.1 Explanation of options .......................................................................................................................74
A.2.2 Input file ............................................................................................................................................76
A.2.3 Output file .........................................................................................................................................76
A.3 OPENCAD Environment Variables............................................................................................. 76
A.4 Error Messages........................................................................................................................... 77

risccpu

good, thanks.

amormio124

下来看看

risccpu

good, thanks.

risccpu

good, thanks.

nelsonafn

谢谢。..................................

hzhou

不错的资料，谢谢了。

forestimber

advance
目录都值得一看

86497689

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菡沁

我都快被这个纠结死了