Berkeley2010最新ADC博士论文

northfish

Time Domain Interference Cancellation for Cognitive Radios and Future Wireless Systems

Contents
List of Figures .................................................................................................................... v
List of Tables..................................................................................................................... ix
Chapter 1 Introduction .............................................................................................................. 1
1.1 Motivation ............................................................................................................ 1
1.1.1 Concept of Cognitive Radio ...................................................................... 1
1.1.1.1 Concept of Cognitive Radio ........................................................... 3
1.1.1.2 Uniqueness of Cognitive Radio Systems ....................................... 4
1.1.2 Future Wideband Radio Systems .............................................................. 7
1.2 Approaches for Interference Cancellation ........................................................... 8
1.2.1 Frequency Domain Cancellation ............................................................... 8
1.2.2 Spatial Domain Cancellation..................................................................... 8
1.2.3 Time Domain Cancellation ..................................................................... 10
Chapter 2 Time domain Interference Cancellation Architecture ............................................ 11
2.1 Mixed Signal Architecture ................................................................................. 13
2.1.1 Feedback Architecture ............................................................................ 13
2.1.2 Feedforward Architecture ....................................................................... 15
2.2 Cancellation Digital Processing ......................................................................... 15
2.2.1 Dual Adaptive Filter (AF) ....................................................................... 16
2.2.2 Processing Gain and Interference Attenuation ........................................ 16
2.2.3 CR Signal Protection ............................................................................... 18
iii
2.3 Performance Evaluation and System Design Specification ............................... 19
2.3.1 SINR after Attenuation ........................................................................... 21
2.3.2 Residue Signal Analysis .......................................................................... 22
2.3.2.1 Ratio of Signal Peak to Residue Peak .......................................... 22
2.3.2.2 Residue Power Analysis ............................................................... 23
2.3.3 Overall EBDR for Different SIR............................................................. 24
2.3.4 System Specification for Cancellation ADC and DAC .......................... 26
2.4 Conclusion ......................................................................................................... 26
Chapter 3 Digital Signal Processing In Interference Cancellation.......................................... 27
3.1 System Model .................................................................................................... 28
3.2 Adaptive Filter Approaches ............................................................................... 30
3.2.1 Assumptions ............................................................................................ 30
3.2.2 Single Adaptive Filter Approach ............................................................ 30
3.2.3 Dual adaptive Filter approach ................................................................. 32
3.2.4 Performance Comparison of the Two Approaches ................................. 35
3.2.4.1 Variation of MSE with SIR .......................................................... 35
3.2.4.2 Variation of BER with SIR .......................................................... 36
3.2.4.3 Variation of BER with Bandwidth Ratio ..................................... 37
3.3 Equalizer ............................................................................................................ 37
3.3.1 Linear Adaptive Equalizer ...................................................................... 38
3.3.2 Decision feedback equalizer ................................................................... 38
3.4 Combining Interference Cancellation and Equalizer Blocks ............................. 40
3.4.1 Performance in the presence of noise...................................................... 41
3.4.2 Effect of SIR on overall system performance ......................................... 41
3.5 Conclusion ......................................................................................................... 42
Chapter 4 High Speed ADC .................................................................................................... 43
4.1 ADC Architecture .............................................................................................. 44
iv
4.1.1 Asynchronous Processing ....................................................................... 45
4.1.2 Architecture ............................................................................................. 46
4.2 Metastability Issue and Error Correction ........................................................... 48
4.3 Circuit Implementation ...................................................................................... 50
4.3.1 Critical Path and Reset Loop .................................................................. 51
4.3.2 Comparator Design ................................................................................. 52
4.3.3 Semi-closed Loop Digital Circuits .......................................................... 53
4.3.4 DAC Design and Non-Binary Capacitance Array .................................. 55
4.3.5 Opposite-Phase Clocks for Time Interleaving ........................................ 59
4.4 Measurement Results ......................................................................................... 59
4.5 Summary ............................................................................................................ 65
Chapter 5 System Demonstration............................................................................................ 66
5.1 Subtractor and Gain Stage .................................................................................. 66
5.2 DAC ................................................................................................................... 68
5.3 Analog Delay Line ............................................................................................. 70
5.3.1 First and Second Order Analog Delay Cell............................................. 71
5.3.2 Digital Fractional Delay Filters ............................................................... 76
5.4 System Test Bed ................................................................................................. 77
Chapter 6 Conclusions ............................................................................................................ 83
Bibliography ............................................................................................................................. 85

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mynameiswtx

Berkeley2010最新ADC博士论文

air7619

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macaren

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