来自于OPENCORE的Verilog语言的embedded_risc软核

zhalvin · 发表于 2010-5-11 09:41:10

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本帖最后由 zhalvin 于 2010-5-11 09:45 编辑

来自于OPENCORE的Verilog语言的embedded_risc软核
SOC设计，包含比较多的内容。可以作为学习参考代码。比较有价值
顶层文件描述：
MODULE:  Top Level System On A Chip Design
FILE NAME: soc.v
DATE:  May 7th, 2002
AUTHOR:  Hossein Amidi
COMPANY:
CODE TYPE: Register Transfer Level
DESCRIPTION: This module is the top level RTL code of System On a Chip Verilog code.
It will instantiate the following blocks in the ASIC:
1) Vertex STARTUP
2) DLL
3) RISC uProcessor
4) DMA Cntrl
5) LRU Data Cache
6) LRU Instruction Cache
7) Bus Arbiter
8) UART
9) Timer
10)  Flash Controller
11) SDRAM Controller
Hossein Amidi
(C) May 2002

zhalvin · 发表于 2010-5-11 09:45:32

module soc( // Inputs
clk,
reset,
irq,
ser_rxd,
flash_datain,
mem_datain,
// Outputs
pll_lock,
addr,
cs,
ras,
cas,
we,
dqm,
cke,
ba,
pllclk,
halted,
ser_txd,
flash_cle,
flash_ale,
flash_ce,
flash_re,
flash_we,
flash_wp,
flash_rb,
flash_irq,
flash_dataout,
mem_dataout,
mem_addr,
mem_req,
mem_rdwr,
// Inouts
dq
);

zhalvin · 发表于 2010-5-11 09:47:00

bus_arbiter bus_arbiter0( // Input
.reset(reset),
.clk0(clk0),
.bus_request(bus_request),
.dma_dataout(dma_wr_dataout),
.dma_addr(dma_rd_addr),
.dma_cmd(dma_rd_cmd),
.dcache_dataout(dcache_dataout),
.dcache_addr(dcache_addr),
.dcache_cmd(dcache_cmd),
.icache_dataout(icache_dataout),
.icache_addr(icache_addr),
.icache_cmd(icache_cmd),
.sdram_dataout(sdram_dataout),
// Output
.bus_grant(bus_grant),
.dma_datain(dma_wr_datain),
.dcache_datain(dcache_datain),
.icache_datain(icache_datain),
.sdram_addr(sdram_addr),
.sdram_cmd(sdram_cmd),
.sdram_datain(sdram_datain)
);

uart uart0(// Input
.reset(reset),
.clk0(clk0),
.uart_addr(dma_wr_addr),
.uart_host_addr(host_addr),
.uart_host_cmd(host_cmd),
.uart_cmd(dma_rd_cmd),
.uart_host_datain(uart_host_dataout),
.uart_cs(uart_cs),
.uart_rd(uart_rd),
.uart_wr(uart_wr),
.ser_rxd(ser_rxd),
.uart_datain(dma_rd_dataout),
// Output
.ser_txd(ser_txd),
.uart_host_dataout(uart_host_datain),
.uart_dataout(dma_rd_datain)
);

timer timer0( // Input
.reset(reset),
.clk0(clk0),
.timer_host_datain(timer_host_dataout),
.timer_cmd(host_cmd),
.timer_addr(host_addr),
// Output
.timer_host_dataout(timer_host_datain),
.timer_irq(timer_irq)
);

flash_ctrl flash_ctrl0(// Inputs
.reset(reset),
.clk0(clk0),
.flash_host_addr(host_addr),
.flash_host_cmd(host_cmd),
.flash_host_dataout(flash_host_dataout),
.flash_datain(flash_datain),
// Outputs
.flash_host_datain(flash_host_datain),
.flash_cle(flash_cle),
.flash_ale(flash_ale),
.flash_ce(flash_ce),
.flash_re(flash_re),
.flash_we(flash_we),
.flash_wp(flash_wp),
.flash_rb(flash_rb),
.flash_irq(flash_irq),
.flash_dataout(flash_dataout)
);

sdram_ctrl sdram_ctrl0(// Inputs
.clk0(clk0),
.clk0_2x(clk0_2x),
.reset(reset),
.paddr(sdram_addr),
.cmd(sdram_cmd),
.dm(host_dm),
.datain(sdram_datain),
// Outputs
.cmdack(cmdack),
.addr(addr),
.cs(cs),
.ras(ras),
.cas(cas),
.we(we),
.dqm(dqm),
.cke(cke),
.ba(ba),
.dataout(sdram_dataout),
// Inouts
.dq(dq)
);