ESD Protection Design for Circuit with Mixed-Voltage I/O(M.D Ker)

semico_ljj

ESD Protection Design for CMOS Integrated Circuits
with Mixed-Voltage I/O Interfaces

Ming-Dou Ker
Institute of Electronics
National Chiao-Tung University
Hsinchu, Taiwan
mdker@ieee.org

Abstract— With consideration on the gate-oxide reliability, the
new ESD protection design with ESD bus for 1.2/2.5-V mixedvoltage
I/O interfaces is reported by using the new proposed
high-voltage-tolerant power-rail electrostatic discharge (ESD)
clamp circuit. This proposed power-rail ESD clamp circuit
with only 1.2-V low-voltage NMOS/ PMOS devices can be
operated under the 2.5-V input conditions without suffering
the gate-oxide reliability issue. The experimental results in a
0.13-􀈝m CMOS process have confirmed that the proposed
power-rail ESD clamp circuit has high human-body-model
(HBM) and machine-model (MM) ESD robustness and fast
turn-on speed. The proposed power-rail ESD clamp circuit is
an excellent ESD protection solution to the mixed-voltage I/O
interfaces.

rachel0131

thanks for sharing

yuchungwei

謝謝你的分享

liuzhieetop

belamy

待业

duling653

这个文件已经被损坏了,看不了

雨丝

好书啊

xiongherui

thanks for sharing

suqiang0303

谢谢楼主，正需要呢！！！！！！！

aak

還不錯, 幫忙回覆一下 ~