Design technique of fractional-N Delta-Sigma frequency synthesizer

hi_china59

Design technique of fractional-N Delta-Sigma frequency synthesizer for wireless communication in 0.5um silicon germanium
TABLE OF CONTENTS
Page
Abstract   . . . . . . . . . II
Acknowledgements   v
Vita  . . . . . . . . . . . . VI
List of Tables   . . . . x
List of Figures   . . . . xi
Chapters:
1. Introduction ............................................ . 1
1.1 Research Objective . . . . . . . . . . . . . . . . . 2
1.2 Organization................................................ 2
2. Frequency Synthesis Techniques in RF Communications ................. 5
2.1 Phase-Locked Loop . . . . . . . . . . . . . . . . 6
2.1.1 Basic Topology and Operating Principle. . . . .. . . . . . . . . . . . . 6
2.1.2 Theoretical View of Phase-Locked Loop. . . . . .. . . . . . . . . . . 9
2.1.3 Fundamental PLL Mathematical Model. . . . . .. . . . . . . . . . .. 14
2.2 Direct Digital Frequency Synthesizer . . 19
2.2.1 Operation Theory .................................... 20
2.3 The Comparison ofPLL and DDS .............................. 23
3. Phase Noise Properties of Phase-Locked Loop. . .. . . . . . . . . . . . .. 26
3.1 Phase Noise . . . . . . . . . . . . . . . . . . . . . .. 27
3.2 Phase Noise of the Building Blocks in PLL . . . . . . . . . . . . . . .. 31
4. Settling Behavior otPhase-Locked Loop .............................. 38
4.1 The Stability and Settling Behavior . . . . 38
4.2 Optimal Settling and Filter BandwidthlLoop Gain otPLL .  . . . . . . . . 41
5. Fractional-NFrequency Synthesis with Delta Sigma Modulator .......... , . 46
5.1 Delta-Sigma Modulator . . . . . . . . . . . . . 48
5.2 The Operation of Fractional-N Frequency Synthesizer. . . . . . . . . . 51
6. Frequency Dividers . . . . . . . . . . . . . . . . . . . . . 55
6.1 Basic Digital Cells of the Radio Frequency Divider. . .. . . . . . . . . 55
6.2 RF Divider . . . . . . . . . . . . . . . . . . . . . . . 59
6.3 RF Input Buffer Amplifier . . . . . . . . . . . 69
6.3.1 Impedance Matching . . . . . . . . . 70
6.3.2 Gain Stage and Output Buffer . . 75
6.4 Reference Divider . . . . . . . . . . . . . . . . . 77
7. Frequency Phase Detector/Charge Pump . . . . 79
7.1 Phase Frequency Detector ...................... '.............. 79
7.2 Charge Pump . . . . . . . . . . . . . .. ............................... 90
8. Prototype Experiments . . . . . . . . . . . . . . . . . . 95
8.1 Low-Power Handset Syntheiszer ......... " .................... 95
8.1.1 Theoretical Design and Simulation. . . . . . . . . . . . . . . . . 98
8.1.2 Experim.ental Results . . . . . . . . 105
8.2 Fast-Locking Low-Power Basestation Syntheiszer . . . . . . . . . . . . 112
8.2.1 Experimental Results of Base station Synthesizer. . . . . . . . 113
9. Conclusions  117
9.1 Present Design review  . . . . . . . . . . . . . 118
9.2 Challenge and Future Research . . . . . . 120
Bibliography   . . . 122

sssh

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lgy737

thanks

lgy737

thanks

lvyuze

谢谢楼主啊

allenlu2006

非常感謝

mmic1978

thank you for sharing~~

Shangyih

Reference for frequency synthesizer

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kankankankankan

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