This application note is written for logic designers who are new to HDL verification flows, and
who do not have extensive testbench-writing experience.[local]1[/local][local]1[/local]
Testbenches are the primary means of verifying HDL designs. This application note provides
guidelines for laying out and constructing efficient testbenches. It also provides an algorithm to
develop a self-checking testbench for any design.
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发表于 2009-10-21 08:30:43
